KDC5514EVALZ Intersil, KDC5514EVALZ Datasheet - Page 32

• Manufacturer Part Number: KDC5514EVALZ
• Description: DAUGHTER CARD FOR KAD5514
• Manufacturer: Intersil
• Series: FemtoCharge™r

Specifications of KDC5514EVALZ

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 250M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 1.47 Vpp
• Power (typ) @ Conditions: 429mW @ 250MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: KAD5514P-25, KMB001 Motherboard
• For Use With: KMB001LEVAL - MOTHERBOARD FOR LVDS ADC CARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: KDC5514EVAL; KDC5514EVAL

Revision History
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
10/23/08
11/13/08
7/30/08
1/15/09
2/25/09
8/17/09
8/24/09
DATE
REVISION
FN6804.0
FN6804.0
FN6804.0
FN6804.1
FN6804.2
FN6804.2
Rev 0a
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
For information regarding Intersil Corporation and its products, see www.intersil.com
Converted to intersil template. Assigned file number FN6804. Rev 0 - first release (as preliminary datasheet) with new
Preliminary Datasheet Update
file number.
Applied Intersil Standards
P1; revised Key Specs
P2; added Part Marking column to Order Info
P4; moved Thermal Resistance to Thermal Info table and added Theta JA note 3 per packaging
P4-8; revisions throughout spec tables. Added notes 9 and 10 to Switching Specs.
P9; revised function for Pin 22 OUTMODE, Pin 23 NAPSLP and Pin 16 CLKDIV
P11; revised function for Pin 16 NAPSLP
P13-15; Added Typical Performance curves
P17; added Figs 25-26
P17; User Initiated Reset - revised 2nd sentence of 1st paragraph
P18; Serial Peripheral Interface- 1st paragraph; revised 4th sentence
P19; revised Nap/Sleep; revised 3rd sentence of 1st paragraph
P21; Serial Peripheral Interface- added 3rd sentence to 4th paragraph
P23; Address 0x24: Gain_Fine; added 2 sentences to end of 1st paragraph.
Revised Table 8
P24; removed Figure (PHASE SLIP: CLK÷2 MODE, fCLOCK = 500MHz)
Address 0x71: Phase_slip; added sentence to end of paragraph
P27; Changed AVDD to OVDD in Fig 46
P27; revised Fig 45
P27; Table 16; revised Bits7:4, Addr C0
Throughout; formatted graphics to Intersil standards
Corrected 48 QFN pin description table on page 11 to show OVDD pins from “20, 27” to “20, 37”.
Changed “odd” bits N in Figure 1A - DDR to “even” bits N, Replaced POD L48.7x7E due to changed dimension from
“9.80 sq” to “6.80” sq. in land pattern
1) Added nap mode, sleep mode wake up times to spec table
2) Added CSB,SCLK Setup time specs for nap, sleep modes
3) Added section showing 72pin/48pin package feature differences and default state for clkdiv,outmode,outfmt page 30
4) Changed SPI setup time specs wording in spec table
5) Added ‘Reserved’ to SPI memory map at address 25H
6) Renumbered Notes
7) Added test platform link on page 30
8) Added ddr enable note13 for 48 pin/72 pin options
9) Changed pin description table for 72/48 pin option, added DDR notes
10) changed multi device note in spi physical interface section to show 3-wire application.page 23
11) Update digital output section for ddr operation page 20
12) change to fig25and fig26 and description in text
13) Added connect note for thermal pad
14) Formatted Figures 25 and 26 with Intersil Standards,
15) Change to SPI interface section in spec table, timing in cycles now, added write, read specific timing specs.
16) Updated SPI timing diagrams, Figures 37, 38
17) Updated wakeup time description in “Nap/Sleep” on page 21.
18) Removed calibration note in spec table
19) Changed label in fig 46
20) Updated cal paragraph in user initiated reset section per DC.
1) Changed tDHR spec needs from 1.5 to 3 cycles.
2) Moved 20k ohm label in fig 46 closer to resistor connected to ovdd
32
KAD5514P
CHANGE
September 10, 2009
FN6804.2