DS26334DK Maxim Integrated Products, DS26334DK Datasheet - Page 67

• Manufacturer Part Number: DS26334DK
• Description: KIT DESIGN FOR DS26334
• Manufacturer: Maxim Integrated Products

Specifications of DS26334DK

• Main Purpose: Telecom, Line Interface Units (LIUs)
• Utilized Ic / Part: DS26334
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address (LIUs 1–8):
Bit #
Name
Default
Register Address (LIUs 9–16):
Bit #
Name
Default
Bits 7 to 0: Individual Jitter Attenuator FIFO Depth Select n (IJAFDSn). When this bit is set for LIUn the jitter
attenuator FIFO depth will be 128 bits. When reset the jitter attenuator FIFO depth will be 32 bits. Note that if the
GC.IJAFDS register bit is set, this register will be ignored.
Register Name:
Register Description:
Register Address (LIUs 1–8):
Bit #
Name
Default
Register Address (LIUs 9–16):
Bit #
Name
Default
Bits 7 to 0: Individual Jitter Attenuator FIFO Limit Trip n (IJAFLTn). Set when the jitter attenuator FIFO
reaches to within 4 bits of its useful limit for transmitter n. This bit will be cleared when read.
Register Name:
Register Description:
Register Address (LIUs 1–8):
Bit #
Name
Default
Register Address (LIUs 9–16):
Bit #
Name
Default
Bits 7 to 0: Individual Short-Circuit Protection Disable n. (ISCPDn). When this bit is set the short-circuit
protection is disabled for the individual transmitter n. Note that if the
register will be ignored.
IJAFDS16
IJAFLT16
ISCPD16
IJAFDS8
IJAFLT8
ISCPD8
7
0
7
0
7
0
7
0
7
0
7
0
IJAFDS15
IJAFLT15
ISCPD15
IJAFDS7
IJAFLT7
ISCPD7
6
0
6
0
6
0
6
0
6
0
6
0
IJAFDS
Individual Jitter Attenuator FIFO Depth Select Register
02h
22h
IJAFLT
Individual Jitter Attenuator FIFO Limit Trip Register
03h
23h
ISCPD
Individual Short-Circuit Protection Disable Register
04h
24h
IJAFDS14
IJAFLT14
ISCPD14
IJAFDS6
IJAFLT6
ISCPD6
DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
5
0
5
0
5
0
5
0
5
0
5
0
IJAFDS13
IJAFLT13
ISCPD13
IJAFDS5
IJAFLT5
ISCPD5
67 of 121
4
0
4
0
4
0
4
0
4
0
4
0
IJAFDS12
IJAFLT12
ISCPD12
IJAFDS4
IJAFLT4
ISCPD4
3
0
3
0
3
0
3
0
3
0
3
0
GC.SCPD
IJAFDS11
IJAFLT11
ISCPD11
IJAFDS3
IJAFLT3
ISCPD3
register bit is set, the settings in this
2
0
2
0
2
0
2
0
2
0
2
0
IJAFDS10
IJAFLT10
ISCPD10
IJAFDS2
IJAFLT2
ISCPD2
1
0
1
0
1
0
1
0
1
0
1
0
IJAFDS1
IJAFDS9
IJAFLT1
IJAFLT9
ISCPD1
ISCPD9
0
0
0
0
0
0
0
0
0
0
0
0