EVB8700C SMSC, EVB8700C Datasheet - Page 25

• Manufacturer Part Number: EVB8700C
• Description: BOARD EVAL FOR LAN8700
• Manufacturer: SMSC
• Series: flexPWR™r

Specifications of EVB8700C

• Main Purpose: Interface, Ethernet PHY
• Embedded: No
• Utilized Ic / Part: LAN8700
• Primary Attributes: Single Chip PHY, 8/15 kV ESD Protection
• Secondary Attributes: >150 Meter Cable Drive, HP Auto-MDIX Auto Polarity Correction
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1040; EVB-LAN8700

±15kV ESD Protected MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX Support and flexPWR
Datasheet
SMSC LAN8700/LAN8700i
4.5.4
4.6
4.6.1
4.6.2
Jabber Detection
Jabber is a condition in which a station transmits for a period of time longer than the maximum
permissible packet length, usually due to a fault condition, that results in holding the TX_EN input for
a long period. Special logic is used to detect the jabber state and abort the transmission to the line,
within 45ms. Once TX_EN is deasserted, the logic resets the jabber condition.
As shown in
The MII/RMII block is responsible for the communication with the controller. Special sets of hand-shake
signals are used to indicate that valid received/transmitted data is present on the 4 bit receive/transmit
bus.
The device must be configured in MII or RMII mode. See
on page
MII
The MII includes 16 interface signals:
In MII mode, on the transmit path, the PHY drives the transmit clock, TX_CLK, to the controller. The
controller synchronizes the transmit data to the rising edge of TX_CLK. The controller drives TX_EN
high to indicate valid transmit data. The controller drives TX_ER high when a transmit error is detected.
On the receive path, the PHY drives both the receive data, RXD[3:0], and the RX_CLK signal. The
controller clocks in the receive data on the rising edge of RX_CLK when the PHY drives RX_DV high.
The PHY drives RX_ER high when a receive error is detected.
RMII
The SMSC LAN8700/LAN8700i supports the low pin count Reduced Media Independent Interface
(RMII) intended for use between Ethernet PHYs and Switch ASICs. Under IEEE 802.3, an MII
comprised of 16 pins for data and control is defined. In devices incorporating many MACs or PHY
interfaces such as switches, the number of pins can add significant cost as the port counts increase.
The management interface (MDIO/MDC) is identical to MII. The RMII interface has the following
characteristics:
MAC Interface
transmit data - TXD[3:0]
transmit strobe - TX_EN
transmit clock - TX_CLK
transmit error - TX_ER/TXD4
receive data - RXD[3:0]
receive strobe - RX_DV
receive clock - RX_CLK
receive error - RX_ER/RXD4
collision indication - COL
carrier sense - CRS
It is capable of supporting 10Mb/s and 100Mb/s data rates
A single clock reference is sourced from the MAC to PHY (or from an external source)
It provides independent 2 bit wide (di-bit) transmit and receive data paths
It uses LVCMOS signal levels, compatible with common digital CMOS ASIC processes
26.
Table
5.31, bit 1.1 indicates that a jabber condition was detected.
DATASHEET
®
25
Technology in a Small Footprint
Section 4.6.3, "MII vs. RMII Configuration,"
Revision 2.2 (12-04-09)