MAX9209EVKIT+ Maxim Integrated Products, MAX9209EVKIT+ Datasheet - Page 4

• Manufacturer Part Number: MAX9209EVKIT+
• Description: KIT EVAL FOR MAX9209
• Manufacturer: Maxim Integrated Products

Specifications of MAX9209EVKIT+

• Main Purpose: Interface, Serializer, Deserializer (SERDES)
• Utilized Ic / Part: MAX9209
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MAX9209/MAX9244 Evaluation Kit
The MAX9209/MAX9244 EV kit provides a proven
design to evaluate the MAX9209 21-bit programmable
DC-balanced serializer and the MAX9244 21-bit deseri-
alizer with programmable spread spectrum and DC
balance. The MAX9209 serializes 21 bits of LVCMOS/
LVTTL parallel input data to three LVDS outputs. The
MAX9244 deserializes the three LVDS input data from
the MAX9209 and transforms it back to 21-bit LVC-
MOS/LVTTL parallel data.
The MAX9209 accepts 21-bit parallel data at LVC-
MOS/LVTTL. The 21-bit pattern is supplied to the EV kit
by connecting a data generator to the three 20-pin
headers (H1, H2, and H3), or by connecting selected
H1, H2, and H3 pins to high/low LVCMOS/LVTTL
states. See Tables 2, 3, and 4 for input bit locations for
H1, H2, and H3.
Table 2. Input Bit Locations for BIT0–BIT6
Table 3. Input Bit Locations for BIT7–BIT13
Table 4. Input Bit Locations for BIT14–BIT20
Table 5. Input/Output Clock Locations
Table 6. Output Bit Locations for BIT10–BIT20
Table 7. Output Bit Locations for BIT0–BIT9
4
Input (H6)
Input (H5)
SIGNAL
SIGNAL
Detailed Description of Hardware
Input (H1)
Input (H2)
Input (H3)
_______________________________________________________________________________________
SIGNAL
SIGNAL
SIGNAL
TXCLK_IN
SIGNAL
BIT10
H6-13
H5-3
BIT0
BIT14
BIT0
H1-1
BIT7
H2-1
H3-1
BIT11
H5-5
H6-15
BIT1
BIT12
H5-7
BIT15
BIT1
H1-3
BIT8
H2-3
H3-3
H6-17
BIT2
DESIGNATION
Input Signals
H4-15
BIT13
H5-9
H6-19
BIT3
BIT16
BIT2
H1-5
BIT9
H2-5
H3-5
BIT14
H5-11
H6-21
BIT4
The MAX9244 outputs 21-bit parallel data at
LVCMOS/LVTTL levels on 40-pin headers H5 and H6.
To sample the 21-bit pattern, connect a logic analyzer
or data-acquisition system to H5 and H6. See Tables 6
and 7 for the output bit locations on the 40-pin headers
(H5 and H6).
The MAX9209 operates at a parallel clock frequency of
8MHz to 34MHz in DC-balance mode by moving the
shunt of JU4 to the 1-2 position. The MAX9244 oper-
ates at a parallel clock frequency of 16MHz to 34MHz
in DC-balance mode by moving the shunt of JU9 to the
2-3 position.
The MAX9209 operates at a parallel clock frequency of
10MHz to 40MHz in non-DC-balance mode by moving
the shunt of JU4 to the 2-3 position. The MAX9244
operates at a parallel clock frequency of 10MHz to
40MHz in non-DC-balance mode by moving the shunt
of JU9 to the 1-2 position.
BIT15
H5-13
BIT10
BIT17
BIT3
H1-7
H2-7
H3-7
DC-Balance and Non-DC-Balance Modes
H6-23
BIT5
BIT16
H5-15
H6-25
BIT11
BIT6
BIT18
BIT4
H1-9
H2-9
H3-9
BIT17
H5-17
H6-27
BIT7
BIT18
H5-19
H1-11
BIT12
H2-11
BIT19
H3-11
BIT5
Output Signals
H6-29
BIT8
BIT19
H5-21
H1-13
BIT13
H2-13
BIT20
H3-13
BIT6
H6-31
BIT20
H5-23
BIT9