CLINK3V48BT-133 National Semiconductor, CLINK3V48BT-133 Datasheet - Page 14

• Manufacturer Part Number: CLINK3V48BT-133
• Description: BOARD EVAL FOR DS90CR485, 486
• Manufacturer: National Semiconductor

Specifications of CLINK3V48BT-133

• Main Purpose: Interface, SerDes (Serializer / De-Serializer)
• Embedded: No
• Utilized Ic / Part: DS90CR485, DS90CR486
• Primary Attributes: Serializes 48 LVCMOS/LVTTL to 8 LVDS, 66 ~ 133 MHz
• Secondary Attributes: Transmits over 2 Meter 3M MDR LVDS Cable
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

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Applications Information
CONFIGURATION 1
DS90CR481/483 and DS90CR484 with DC Balance ON
(BAL = High, 33MHz to 80MHz) − The DS_OPT pin at the
input of the transmitter DS90CR481/483 must be applied low
for a minimum of four clock cycles in order for the receiver to
complete the deskew operation. The input to the DS_OPT
pin can be applied at any time after the PLL has locked to the
input clock frequency. In this particular setup, the "DESKEW"
pin on the receiver DS90CR484 must set High.
CONFIGURATION 2
DS90CR481/483 and DS90CR486 with DC Balance ON
(BAL=High, CON1=High, 66MHz to 112MHz) − The
DS_OPT pin at the input of the transmitter DS90CR481/483
can be set to High OR Low when power up. The period of
this input to the DS_OPT pin must be at least 20ms (TX and
RX PLLs lock time) plus 4096 clock cycles in order for the
receiver to complete the deskew operation. The "DESKEW"
and CON1 pins on the receiver DS90CR486 must be tied to
High for this setup.
CONFIGURATION 3
DS90CR481/483 and DS90CR486 with DC Balance OFF
(BAL=Low, CON1=High, 66MHz to 112MHz) − The input to
the DS_OPT pin of the transmitter DS90CR481/483 in this
configuration is completely ignored by the transmitters. In
order to initialize the deskew operation on the receiver
DS90CR486, data and clock must be applied to the trans-
mitter when power up. The "DESKEW" and CON1 pins on
the receiver DS90CR486 must be tied to High for this setup.
CONFIGURATION 4
DS90CR485 and DS90CR484 with DC Balance ON
(BAL=High, 66MHz to 80MHz) − The DS_OPT pin at the
input of the transmitter DS90CR485 must be applied low for
FIGURE 11. Deskew Configuration Setup Chart
(Continued)
14
a minimum of four clock cycles in order for the receiver to
complete the deskew operation. The input to the DS_OPT
pin can be applied at any time after the PLL has locked to the
input clock frequency. In this setup, the "DESKEW" pin on
the receiver DS90CR484 must set High.
CONFIGURATION 5
DS90CR485 and DS90CR486 with DC Balance ON
(DS90CR486’s BAL=Hiigh and CON1=High, 66MHz to
133MHz) − The DS_OPT pin at the input of the transmitter
DS90CR485 can be set to High OR Low when power up.
The period of this input to the DS_OPT pin must be at least
20ms (TX and RX PLLs lock time) plus 4096 clock cycles in
order for the receiver to complete the deskew operation. The
"DESKEW" and CON1 pins on the receiver DS90CR486
must set High.
CONFIGURATION 6
DS90CR485 and DS90CR486 with DC Balance OFF
(DS90CR486’s BAL=Low, CON1=High, 66MHz to 133MHz)
−The input to the DS_OPT pin of the transmitter
DS90CR485 in this configuration is completely ignored. In
order to initialize the deskew operation on the receiver
DS90CR486, data and clcok must be applied to the trans-
mitter when power up. The "DESKEW" and CON1 pins on
the receiver DS90CR486 must set High.
DESKEW NOT SUPPORTED
Deskew function is NOT supported in these configuration
setups. The deskew feature is only supported with DC Bal-
ance ON (BAL=High) for DS90CR484. Note that the deskew
function in the DS90CR486 works in both DC Balance and
NON-DC Balance modes.
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