CLINK3V48BT-133 National Semiconductor, CLINK3V48BT-133 Datasheet - Page 7

• Manufacturer Part Number: CLINK3V48BT-133
• Description: BOARD EVAL FOR DS90CR485, 486
• Manufacturer: National Semiconductor

Specifications of CLINK3V48BT-133

• Main Purpose: Interface, SerDes (Serializer / De-Serializer)
• Embedded: No
• Utilized Ic / Part: DS90CR485, DS90CR486
• Primary Attributes: Serializes 48 LVCMOS/LVTTL to 8 LVDS, 66 ~ 133 MHz
• Secondary Attributes: Transmits over 2 Meter 3M MDR LVDS Cable
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Power & Ground
General Power/Ground Recommendations
A solid power/ground system is the foundation on which a reliable interconnect system is built. Design circuit board
layout and stack-up for the system to provide noise-free power to the device. Good layout practice will separate
high frequency and high level inputs and outputs to minimize unwanted stray noise pickup, feedback, and interfer-
ence. Power system performance may be greatly improved by using thin dielectrics (4 to 10 mils) for power/ground
sandwiches. This increases the intrinsic capacitance of the PCB power system, which improves power supply filter-
ing—especially at high frequencies—making the value and placement of external bypass capacitors less critical.
External bypass capacitors should include both RF ceramic and tantalum electrolytic types. Use RF capacitors in the
range of 0.001 µF to 0.1 µF. Use tantalum capacitors in the range of 2.2 µF to 10 µF. The voltage rating of tantalum
capacitors should be at least 3 (5 preferred) times the power supply voltage being used.
It is recommended practice to use two vias at each power/ground pin as well as all RF bypass capacitor terminals.
Dual vias reduce the interconnect inductance by up to half, thereby extending the effective range of bypass compo-
nents. Locate RF capacitors as close as possible to the supply pins and use wide, low impedance traces—not 50-
Ohm traces. Surface mount capacitors are recommended due to lower parasitics. When using multiple capacitors
per supply pin, locate the smallest value closest to the supply pin. A bulk capacitor is recommended at the point of
power entry. This is typically in the range of 50 µF to 100 µF and will smooth low frequency noise.
Some devices have separate power/ground pins for different portions of the circuits to isolate switching noise
50 Ω
effects between different blocks. Connecting these to separate power/ground planes on the PCB is typically not
required. Pin description tables typically describe which blocks are connected to which power/ground pins. In some
cases, an external filter may be used to provide clean power to sensitive circuits such as PLLs.
Channel Link Recommendations
General device-specific bypassing recommendations are given below. Actual best practice depends on other board and system level criteria in-
cluding board density, power rail and power supply type, and the supply needs of other integrated circuits on the board. When minimizing supply
noise, priority should be given in this order: PLL, LVDS, and then digital V
pins.
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PLL Supply
The PLL V
pins supply the PLL circuits. PLLs require a clean supply—less than 100 mV noise peak-to-peak—for the minimization of jitter and
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best link margin. PLL V
noise in the frequency range 200 kHZ to 3 MHz can increase jitter and reduce noise margins. Certain power supplies may
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have switching frequencies or high harmonic content in this range. If this is the case, filtering of this noise spectrum may be required. A notch
filter response is best to provide stable V
, suppression of the noise band, and good high frequency response (clock fundamental). This may be
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accomplished with a CRC or CLC pie filter. If employed, a separate pie filter is recommended for each PLL to minimize the voltage drop due to
series resistance. Separate board power planes for each PLL V
pin is not required.
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LVDS Supply
The LVDS V
pins supply the LVDS circuits. Due to the nature of the Channel Link, large currents are not drawn through these pins and a 0.1 µF
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capacitor is normally sufficient for these pins. If space is available, a 0.01 µF capacitor may be used in parallel with the 0.1 µF capacitor for addi-
tional high frequency filtering. Connect the LVDS ground to the cable ground to provide a return path for any common (even) mode currents. Most
of the LVDS current is odd-mode and returns within the pair, though a small amount of odd-mode current may be present due to coupled noise
and the cable ground should return through a low impedance path to LVDS ground pins.
Digital Supply
The digital V
pins supply the digital portion of the device and also the receiver TTL output drivers. The receiver digital V
is more critical than
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the transmitter digital V
because it must power the receiver outputs during multiple output switching conditions. Bypassing for receiver digital
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Vcc can be estimated as follows:
Total digital bypassing capacitance = (number TTL receiver outputs/digital VCC pins) x (max short circuit current x output rise time) ÷ (max allowed VCC droop, typically 50 mV)