SI5100-EVB Silicon Laboratories Inc, SI5100-EVB Datasheet - Page 5

• Manufacturer Part Number: SI5100-EVB
• Description: BOARD EVALUATION FOR SI5100
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5100-EVB

• Main Purpose: Interface, SONET/SDH, Transceiver
• Utilized Ic / Part: SI5100
• Wireless Frequency: 2.4 GHz
• Operating Voltage: 1.8 VDC
• Output Power: 1.2 W
• Operating Temperature Range: - 20 C to + 85 C
• For Use With/related Products: Si5100
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1136

Functional Description
The Si5100-EVB and Si5110-EVB motherboard and
daughter card sets simplify characterization of the OC-
48/STM-16 and FEC transceiver devices by providing
convenient
performance can be evaluated in various modes by
following the “Basic Test Setup” section.
Power Supply
The transceiver device can be powered from a single
1.8 V supply or seperate 1.8 V and 3.3 V supplies.
When the additional 3.3 V supply is applied, the status
outputs are LVTTL compatible. The daughter card can
be configured for either mode of operation by setting the
VDD_IO SEL jumper as shown in Figure 4.
Control Inputs
The device control inputs are located on the
motherboard and daughter card. Signals with equivalent
module functions are routed to the motherboard header,
JP1. Signals specific to the transceiver are routed on
the daughter card to jumpers JP1 and JP2. In both
cases, the signal is routed to the center pin of a three
pin group where the adjacent pins are power and
ground. The device inputs are pulled high or low so that
leaving a signal unconnected will not harm the device.
Status Outputs
The device status outputs are located on the
motherboard and daughter card. Signals with equivalent
module functions are routed to the motherboard header,
JP2. Signals specific to the transceiver are routed on
the daughter card to headers JP3 and JP4. In both
cases, the signal is routed to a header pin adjacent to a
ground pin.
VDD_IO
VDD_IO
Figure 4. VDD_IO Selection Jumpers
SEL
SEL
access
For 3.3 V/1.8 V operation
For 1.8 V operation only
1.8 V
3.3 V
1.8 V
3.3 V
to
the
device
I/Os.
Preliminary Rev. 0.5
Device
Data I/O Signals
The serial 2.5 Gbps data and 2.5 GHz clock paths are
routed as coplanar differentially-coupled microstrip
transmission lines on the daughter card. These three
signals (RXDIN, TXCLKOUT, and TXDOUT) are ac
coupled to standard SMA jacks for ease in connection
to industry standard test equipment. Take care when
connecting cables to these jacks. Use a standard SMA
torque wrench to minimize reflections at the cable-to-
jack interface. Finally, match all differential connections
in length to minimize phase differences between the
positive and negative terminals.
Differential Parallel Data and
Clock I/O Signals
The differential parallel data lines are routed through the
300-pin meg-array connector to the motherboard. The
standard loopback motherboard directly couples the
RXDOUT bus to the TXDIN bus. The optional full-
duplex motherboard directly couples the RXDOUT and
TXDIN buses to standard SMA jacks for connection to
industry standard test equipment.
Slice Level, Loss-of-Signal Level, and
Phase Adjust
Voltages present at the Slice Level (SLICELVL), Loss-
of-Signal
(PHASEADJ) pins can be used to adjust the data slicing
level, the loss-of-signal alarm level, and the sampling
phase position, respectively. Because these inputs are
high impedance, simple turn-based potentiometers are
used to apply the control voltage. The Si5100-EVB
provides 50 kΩ potentiometers for each of these inputs:
potentiometer R16 sets the voltage applied to the
SLICELVL pin; R14 sets the voltage applied to the
LOSLVL pin, and R15 sets the voltage applied to the
PHASEADJ pin. The Si5110-EVB also provides 50 kΩ
potentiometers for each of these inputs. Potentiometer
R5 sets the voltage applied to the SLICELVL pin; R3
sets the voltage applied to the LOSLVL pin, and R4 sets
the voltage applied to the PHASEADJ pin. The
potentiometers are connected so the voltage applied
varies from GND to VREF. Refer to the device data
sheet for details on the operation of these inputs.
Basic Test Setup
The configurations listed in Tables 1 and 3 allow easy
setup of the transceiver evaluation system for operation
in the line loopback, full duplex, or diagnostic loopback
modes. Other configurations are supported; however,
operation should first be verified in one of these modes
in order to minimize the number of unknown variables.
Level
Si5100/Si5110-EVB
(LOSLVL)
and
Phase
Adjust
5