EVK-DS40MB200 National Semiconductor, EVK-DS40MB200 Datasheet - Page 9

• Manufacturer Part Number: EVK-DS40MB200
• Description: BOARD EVALUATION DS40MB200
• Manufacturer: National Semiconductor

Specifications of EVK-DS40MB200

• Main Purpose: Interface, 2:1 Multiplexer
• Utilized Ic / Part: DS40MB200
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

V
t
R
R
ΔR
V
POWER DISSIPATION
P
AC CHARACTERISTICS
t
t
t
t
t
t
t
t
RJ
PE
R
F
PLH
PHL
SKP
SKO
SKPP
SM
Symbol
PE
OCM
D
OTSE
OTD
OTSE
Output Pre-Emphasis
Voltage Ratio
20*log(VODPE/VODB)
Pre-Emphasis Width
(Note 8)
Output Termination
Output Differential
Termination
Mis-Match in Output
Termination Resistors
Output Common Mode
Voltage
Power Dissipation
Differential Low to High
Transition Time
Differential High to Low
Transition Time
Differential Low to High
Propagation Delay
Differential High to Low
Propagation Delay
Pulse Skew (Note 8)
Output Skew
(Notes 7, 8)
Part-to-Part Skew
(Note 8)
Mux Switch Time
Device Random Jitter
(Notes 5, 8)
Parameter
R
Running K28.7 pattern at 4 Gbps
PREx_[1:0]=00
PREx_[1:0]=01
PREx_[1:0]=10
PREx_[1:0]=11
x=S for switch side pre-emphasis control
x=L for line side pre-emphasis control
See Figure 1 on waveform.
See Figure 5 for test circuit.
Tested at −9 dB pre-emphasis level, PREx[1:0]=11
x=S for switch side pre-emphasis control
x=L for line side pre-emphasis control
See Figure 4 on measurement condition.
On-chip termination from OUT+ or OUT− to V
On-chip differential termination between OUT+ and
OUT−
Mis-match in output terminations at OUT+ and OUT
−
V
All outputs terminated by 100Ω ±1%.
PREL_[1:0]=0, PRES_[1:0]=0
Running PRBS 2
Measured with a clock-like pattern at 100 MHz,
between 20% and 80% of the differential output
voltage. Pre-emphasis disabled.
Transition time is measured with fixture as shown
in Figure 5, adjusted to reflect the transition time at
the output pins.
Measured at 50% differential voltage from input to
output.
|t
Difference in propagation delay among data paths
in the same device.
Difference in propagation delay between the same
output from devices operating under identical
condition.
Measured from V
loopback control to 50% of the valid differential
output.
See Figure 5 for test circuit.
Alternating-1-0 pattern.
Pre-emphasis disabled.
At 1.25 Gbps
At 4 Gbps
PHL
DD
L
= 100Ω ±1%
= 3.465V
–t
PLH
|
7
IH
-1 pattern at 4 Gbps
Conditions
or V
IL
of the mux-control or
9
CC
Min
125
42
(Note 2)
Typ
200
100
2.7
0.5
0.5
1.8
−3
−6
−9
50
80
80
0
Max
250
200
500
58
20
5
1
2
2
6
2
2
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psrms
psrms
Units
dB
dB
dB
dB
ps
W
ps
ps
ns
ns
ps
ps
ps
ns
%
Ω
Ω
V