DS16EV51-AEVKH National Semiconductor, DS16EV51-AEVKH Datasheet - Page 15
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DS16EV51-AEVKH
Manufacturer Part Number
DS16EV51-AEVKH
Description
BOARD EVAL FOR DS16EV5110A
Manufacturer
National Semiconductor
Specifications of DS16EV51-AEVKH
Main Purpose
Video, Cable Extender
Utilized Ic / Part
DS16EV5110A
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
General Recommendations
The DS16EV5110 is a high performance circuit capable of
delivering excellent performance. Careful attention must be
paid to the details associated with high-speed design as well
as providing a clean power supply. Refer to the LVDS
Owner’s Manual for more detailed information on high-speed
design tips as well as many other available resources avail-
able addressing signal integrity design issues.
PCB LAYOUT CONSIDERATIONS FOR DIFFERENTIAL
PAIRS
The TMDS differential inputs and outputs must have a con-
trolled differential impedance of 100Ω. It is preferable to route
TMDS lines exclusively on one layer of the board, particularly
for the input traces. The use of vias should be avoided if pos-
sible. If vias must be used, they should be used sparingly and
must be placed symmetrically for each side of a given differ-
ential pair. Route the TMDS signals away from other signals
and noise sources on the printed circuit board. All traces of
TMDS differential inputs and outputs must be equal in length
to minimize intra-pair skew.
LLP FOOTPRINT RECOMMENDATIONS
See National application note: AN-1187 for additional infor-
mation on LLP packages footprint and soldering information.
FIGURE 10. Equivalent Output Structure
FIGURE 11. Equivalent Input Structure
15
POWER SUPPLY BYPASSING
Two approaches are recommended to ensure that the
DS16EV5110 is provided with an adequate power supply.
First, the supply (VDD) and ground (GND) pins should be
connected to power planes routed on adjacent layers of the
printed circuit board. The layer thickness of the dielectric
should be minimized so that the VDD and GND planes create
a low inductance supply with distributed capacitance. Sec-
ond, careful attention to supply bypassing through the proper
use of bypass capacitors is required. A 0.1µF bypass capac-
itor should be connected to each VDD pin such that the
capacitor is placed as close as possible to the DS16EV5110.
Smaller body size capacitors can help facilitate proper com-
ponent placement. Additionally, three capacitors with capac-
itance in the range of 2.2µF to 10µF should be incorporated
in the power supply bypassing design as well. These capac-
itors can be either tantalum or an ultra-low ESR ceramic and
should be placed as close as possible to the DS16EV5110.
EQUIVALENT I/O STRUCTURES
Figure 10 shows the DS16EV5110 CML output structure and
ESD protection circuitry.
Figure 11 shows the DS16EV5110 CML input structure and
ESD protection circuitry.
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