ISL55110EVAL1Z Intersil, ISL55110EVAL1Z Datasheet - Page 2

• Manufacturer Part Number: ISL55110EVAL1Z
• Description: EVALUATION BOARD FOR ISL55110
• Manufacturer: Intersil

Specifications of ISL55110EVAL1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Finally the center off position provides a means of
connecting a repetitive signal source to the PD input. This is
so that the user can observe Power Down Enable/Disable
timing. An important note to remember when using the PD -
BNC: 1) Place the switch in Center-Off position. 2) The PD
input is referenced to VDD and ground.
Initial Power Up
Please refer to the device specification for power up
sequencing and current requirements. Also note that the
frequency of operation of each driver will determine the
current needed. There are graphs in the specification
regarding current characteristics.
When first powering up the device, set all power bus inputs
to minimum current levels needed for quiescent operation.
Check the device out statically with DC inputs on the IN_A/
IN_B pins and observe that the OA/OB outputs toggle when
the Input pins rise above and below the logic thresholds.
Please note that these inputs are intended for use by high
speed logic. Avoid slow DC ramps.
VDD current should be ~3.6mA and VH should be less then
100µAmps with no DC loads on the outputs.
FIGURE 3. QFN PACKAGES HAVE BOTH POWER DOWN
FIGURE 2. TSSOP AND QFN EVALUATION BOARDS HAVE
SPDT - CENTER OFF
S1- ENABLE CONTROL
SPDT- CENTER OFF
VDD
GND
AND OUTPUT ENABLE DIGITAL INPUTS
THE SAME POWER DOWN CIRCUITRY
SPDT - CENTER OFF
1
2
3
4
VDD
/ENABLE
PD
IN-B
GND
S1 - POWER DOWN CONTROL
10k
VDD
R7
GND
ISL55110, ISL55111_TSSOP
S2 - POWER DOWN CONTROL
ISL55110, ISL55111_QFN
1
2
3
4
10k
VDD
PD
IN-B
IN-A
GND 11
10k
R7
R8
VH 10
OA 9
OB 12
VDD
2
PD - BNC
GND
GND 7
VDD
OB 8
VH 6
OA 5
PD - BNC
GND
EN - BNC
GND
Application Note 1283
Once static observations check out, you can then increase
power current limits for VCC/VH and apply higher frequency
inputs to the IN_A/IN_B pins.
Layout Information
All evaluation boards have complete silk-screen information
regarding Test points, Jumpers and Component placements.
Schematic Information
Schematics are drawn with physical location in mind. Any
changes in electrical circuitry will be updated in this
document as needed.
Included below are two schematics. ISL55110, ISL55111:
TSSOP dual driver device and ISL55110, ISL55111 QFN
dual driver. Both packages have the Power Down Control,
while the QFN has both Power Down and Enable inputs.
Driver Loads
Component locations C6 to C7 and R3 to R6 are surface
mount locations provided so the user can experiment with
various load configurations.
DRIVER OUT OB
DRIVER OUT OA
DIF+
DIF-
DIF+
DIF-
FIGURE 4. CUSTOM LOAD COMPONENTS
TP-OB
TP-OA
POPULATED
POPULATED
NOT
NOT
C6
C7
R3
R4
0Ω
0Ω
GND
GND
NOT
POPULATED
C8
NOT
POPULATED
C9
R5
0Ω
R6
0Ω
February 13, 2007
OA - BNC
OB - BNC
AN1283.0