SI3000PPT-EVB Silicon Laboratories Inc, SI3000PPT-EVB Datasheet
SI3000PPT-EVB
Specifications of SI3000PPT-EVB
Related parts for SI3000PPT-EVB
SI3000PPT-EVB Summary of contents
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OICE AND ODEC Features Complete voice codec solution includes the following ADC Dynamic Range DAC Dynamic Range 4–12 kHz Sample Rates Microphone Pre-Amp ...
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Si3000 2 Rev. 1.4 ...
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T C ABLE O F ONTENTS Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Si3000 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Temperature 2 Si3000 Supply Voltage, Analog 2,3 Si3000 Supply Voltage, Digital Notes: 1. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values ...
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Table 4. AC Characteristics ( ±5% or 3.3 V ±10 70° Parameter ADC Resolution 1,2 ADC Dynamic Range 3 ADC Total Harmonic Distortion 3.3 ...
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Si3000 Table 4. AC Characteristics (Continued ±5% or 3.3 V ±10 70° Parameter DAC Output Gain Step Size 5 DAC Freq Response 5 DAC Freq Response DAC ...
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Table 6. Switching Characteristics—General Inputs ( ±5% or 3.3 V ±10%, 70° Parameter Cycle Time, MCLK MCLK Duty Cycle Rise Time, MCLK Fall Time, MCLK 2 RESET ...
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Si3000 Table 7. Switching Characteristics—Serial Interface ( ±5% or 3.3 V ±10 70° Parameter Cycle Time, SCLK SCLK Duty Cycle Delay Time, SCLK to FSYNC Delay ...
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Table 8. Digital FIR Filter Characteristics—Transmit and Receive ( ±5% or 3.3 V ±10%, Sample Rate = 8 kHz Parameter Passband (3 dB, HPFD = 1) Passband (3 dB, HPFD = 0) ...
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Si3000 Input Frequency - Hz Figure 3. FIR Receive Filter Response Input Frequency - Hz Figure 4. FIR Receive Filter Passband Ripple For Figures 3–6, all filter plots apply to a sample rate of kHz. The ...
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Input Frequency - Hz Figure 7. IIR Receive Filter Response Input Frequency - Hz Figure 8. IIR Receive Filter Passband Ripple Input Frequency - Hz Figure 9. IIR Transmit Filter Response Input Frequency - Hz Figure 10. IIR Transmit Filter ...
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Si3000 12 Rev. 1.4 ...
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Table 10. Component Values—Typical Application C2,C4,C5,C7,C9,C10 Symbol Value C1,C3,C6,C8 0.1 µ ±20% 10 µ ±20% D1 Motorola MMBD914L J1,J2 Phonejack Stereo JP1 4 Header K1 Relay DPDT L1,L2 Ferrite Bead 0 , 1 ...
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Si3000 2. Functional Description The Si3000 is a highly integrated voice bandwidth audio codec which contains a single 16-bit A/D converter and D/A converter. The analog input path contains a microphone input with selectable gain, a line level input with ...
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Programmable Output Gain/Attenuation Prior to D/A conversion, the Si3000 contains a digital programmable gain/attenuator which provides gain or –34 attenuation in 1.5 dB steps. Level changes only take effect on zero crossings ...
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Si3000 Prim ary D 15 – (Softw are FC Bit ata ata 16 SCLKs 128 SCLKs ...
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CLK ÷ Figure 18. Clock Generation Subsystem (PLL) 2.9. Clock Generation Subsystem The Si3000 contains an on-chip clock generator. Using a single MCLK input frequency, the Si3000 can generate all the desired standard ...
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Si3000 2.9.2. PLL Lock Times The Si3000 changes sample rates very quickly. However, lock time will vary based on the programming of the clock generator. The following relationship describes the boundaries on PLL locking time: PLL lock time < 1 ...
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Control Registers Note: Any register not listed here is reserved and should not be written. Any register bit labelled reserved should be written to zero during writes to the register. Register 0 can be read (always returns 0) and ...
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Si3000 Register 1. Control 1 Bit Name R/W Type Reset settings = 0000_0000 Bit Name Software Reset. Sets all registers to their reset value. Enables chip for normal operation. Note: ...
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Register 2. Control 2 Bit D7 D6 Name Type tings = 0000_0000 Reset Set Bit Name 7:5 Reserved Read returns zero. 4 HPFD High Pass Filter (HPF) Disable HPF disabled 0 = HPF enabled 3 PLL PLL Divide ...
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Si3000 Register 3. PLL1 Divide N1 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 N1 N1. Contains the (value – 1) for determining the output frequency on PLL. Register 4. PLL1 Multiply M1 Bit D7 D6 ...
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Register 5. RX Gain Control 1 Bit D7 D6 LIG Name R/W Type Reset settings = 0100_0111 Bit Name 7:6 LIG Line in Gain gain gain gain 00 ...
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Si3000 Register 6. ADC Volume Control Bit D7 D6 Name Type Reset settings = 0101_1100 Bit Name 7 Reserved Read returns zero. 6:2 RXG RX PGA Gain Control. 11111 = 12 dB 10111 = 0 dB 00000 = –34.5 dB ...
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Register 7. DAC Volume Control Bit D7 D6 Name Type Reset settings = 0101_1100 Bit Name 7 Reserved Read returns zero. 6:2 TXG TX PGA Gain Control. 11111 = 12 dB 10111 = 0 dB 00000 = –34.5 dB LSB ...
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Si3000 Register 8. Status Report Bit D7 D6 SLSC SRSC Name R R Type Reset settings = 0000_0000 Bit Name 7 SLSC SPK_L Short Circuit Indicate short circuit status is detected at left speaker Normal mode ...
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Pin Descriptions: Si3000 Pin # Pin Name 1 SPKRR Speaker Right Output. Analog output capable of driving a 60 load. 2 MBIAS Microphone bias output. 3 HDST Handset Input/Output. Handset analog input/output. 4 SDI Serial Port Data In. ...
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Si3000 Pin # Pin Name 13 V Analog Supply Voltage. A Provides the analog supply voltage to the Si3000. Nominally either 5 or 3.3 V and within 0 GND Ground. Connects to the system digital ground. ...
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Ordering Guide Part Number Si3000-C-FS Si3000-C-GS *Note: Add an “R” at the end of the device to denote tape and reel option. Table 14. Ordering Guide Package Lead-Free SOIC-16 Yes SOIC-16 Yes Rev. 1.4 Si3000 Temp. Range 0 to ...
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Si3000 6. Package Outline: 16-Pin SOIC Figure 19 illustrates the package details for the Si3000. Table 15 lists the values for the dimensions shown in the illustration. Figure 19. 16-Pin Small Outline Integrated Circuit (SOIC) Package Table 15. Package Diagram ...
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SOIC Land Pattern Figure illustrates the recommended land pattern for the Si3000 16-pin SOIC. Table 16 lists the values for the dimensions shown in the illustration. Figure 20. 16-Pin SOIC Land Pattern Diagram Table 16. 16-Pin MSOP ...
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Si3000 8. Package Markings (Top Markings) Codes for the Si3000-C-GS and Si3000-C-FS top marks are as follows Current Year Work Week Die Revision TTTTT = Trace Code 8.1. Si3000-C-GS Top ...
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OCUMENT HANGE IST Revision 1.0 to Revision 1.1 Updated Functional Block Diagram. Removed all B-grade references. Updated Table 4 (AC Characteristics). Updated Figure 14. Removed analog loopback feature description. Revision 1.1 to ...
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