SI3050PPT2-EVB Silicon Laboratories Inc, SI3050PPT2-EVB Datasheet - Page 2

• Manufacturer Part Number: SI3050PPT2-EVB
• Description: BOARD EVAL FOR DAA SI3050/SI3008
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3050PPT2-EVB

• Main Purpose: Telecom, Data Acquisition Arrangement (DAA)
• Utilized Ic / Part: Si3050
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Si3050PPT-EVB
1. Functional Description
The Si3050PPT-EVB provides the telecommunications
system engineer an easy way to evaluate the Si3059/19
solution. Silicon Labs’ DAAs are integrated direct
access arrangements that provide a digital, low-cost,
solid-sate interface to worldwide telephone lines.
Through the patented ISOcap™ technology, the Si3050/
19 eliminates the need for an analog frond end (AFE),
an isolation transformer, relays, opto-isolators, and a 2-
to 4-wire hybrid.
The Si3050PPT-EVB also supports the connection of
multiple devices on an SPI/PCM interface. The
evaluation board provides a straightforward means of
evaluating this feature.
The evaluation board consists of the Si3050PPT-EVB
Si-LINK (mother) board and the Si3050DC-EVB
daughter card. A custom ribbon cable is also provided
to connect to the parallel port of a PC. Contact a Silicon
Laboratories representative for more information.
1.1. Motherboard-Daughter Card Connec-
Si3050DC-EVB
through five sockets, JS1–JS5. JS1 is a 5x2 socket and
JS2 is a 2x2 socket connecting SPI digital signals of the
Si3050. JS3 is a 5x2 socket connection reserved for
future use. JS4 is a 5x2 socket connection that routes
the Vdd regulated supply. JS5 is a 5x2 socket
connection to the PCM digital signals of the Si3050. JS3
is a no-connect in this application.
2
tion
connects
to
the
Si3050PPT-EVB
Rev. 1.0
1.2. Power Supply
Power is supplied to the EVB by means of J1 and J4. J4
is a 2.1 mm power jack that allows the use of a wall
transformer. A 9 V supply/300 mA is typically used, but
the on-board voltage regulator will also work with a dc
voltage between 7.5 V and 20 V. A diode bridge is used
to correct polarity. The on-board regulator, U7, provides
5 V to the call progress circuit, the on-board oscillator,
and other boards daisy chained to the Si3050PPT-EVB.
This 5 V is further regulated to 3.3 V to power the
daughter card and the input/output ports of the FPGA. A
third regulator provides 2.5 V for the core voltage of the
FPGA. J1 is a no-connect in this application.
1.3. Clock Generation
The Si3050 requires an FSYNC, PCLK, and SCLK
input. An on-board oscillator (Y1) is used by the FPGA
to clock all the subsystems as well as generate and
provide the FSYNC, PCLK, and SCLK to the DAA.
FPGA is designed to use a 32.768 MHz oscillator
(included with the board).
1.4. Reset Circuit
The Si3050/19 requires an active low pulse on RESET
following power up and whenever all registers need to
be reset. For development purposes, the Si3050PPT-
EVB includes a reset push button, SW1, that is used by
the FPGA to generate a reset pulse of the DAA.
1.5. Line Connection
J1 is provided to connect the EVB to a standard RJ-11
connector. The system cannot execute an off-hook
command without the phone line connected.
1.6. PC Parallel Port
JP2 and P3 connect through the Silicon Labs custom
ribbon cable to the parallel port of the PC. The parallel
port connection allows the designer to read and write
the DAA registers using the evaluation software
included with the Si3050PPT-EVB.