SI3056SSI1-EVB Silicon Laboratories Inc, SI3056SSI1-EVB Datasheet
SI3056SSI1-EVB
Specifications of SI3056SSI1-EVB
Related parts for SI3056SSI1-EVB
SI3056SSI1-EVB Summary of contents
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Features ! PCM highway data interface µ-law/A-law companding ! ! SPI control interface ! GCI interface ! 80 dB dynamic range TX/RX ! Line voltage ...
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Si3050 2 Rev. 1.0 ...
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Section Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . ...
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Si3050 GCI Highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Electrical Specifications Table 1. Recommended Operating Conditions 1 Parameter Ambient Temperature Si3050 Supply Voltage, Digital Notes: 1. The Si3050 specifications are guaranteed when the typical application circuit (including component tolerance) and any Si3050 and any Si3018/19 are used. See "Typical ...
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Si3050 Table 2. Loop Characteristics = = (V 3 °C for K-Grade, see Figure 1 on page Parameter Symbol DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination ...
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Table 3. DC Characteristics 3 °C for K-Grade Parameter 1 High Level Input Voltage 1 Low Level Input Voltage High Level Output Voltage Low Level Output Voltage ...
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Si3050 Table 4. AC Characteristics = = (V 3 °C for K-Grade Parameter Sample Rate PCLK Input Frequency Receive Frequency Response Receive Frequency Response 1 Transmit Full Scale Level 1,3 Receive ...
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Table 4. AC Characteristics (Continued 3 °C for K-Grade Parameter Transhybrid Balance Transhybrid Balance Two-Wire Return Loss Two-Wire Return Loss Notes: 1. Measured at TIP and RING with ...
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Si3050 Table 6. Switching Characteristics—General Inputs = = (V 3 °C for K-Grade Parameter Cycle Time, PCLK PCLK Duty Cycle Rise Time, PCLK Fall Time, PCLK PCLK Before RESET ...
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Table 7. Switching Characteristics—Serial Peripheral Interface = = (V 3 °C for K-Grade Parameter* Cycle Time SCLK Rise Time, SCLK Fall Time, SCLK Delay Time, SCLK Fall to SDO Active ...
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Si3050 Table 8. Switching Characteristics—PCM Highway Serial Interface = = (V 3 °C for K-Grade Parameter Cycle Time PCLK Valid PCLK Inputs 2 FSYNC Period PCLK Duty Cycle FSYNC ...
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Table 9. Switching Characteristics—GCI Highway Serial Interface = = (V 3 °C for K-Grade Parameter Cycle Time PCLK (Single Clocking Mode) Cycle Time PCLK (Double Clocking Mode) Valid PCLK ...
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Si3050 PCLK FSYNC DRX Figure 6. GCI Highway Interface Timing Diagram (2x PCLK Mode) Table 10. Digital FIR Filter Characteristics—Transmit and Receive = = (V 3.0 to 3.6 V, Sample Rate 8 kHz Parameter Passband ...
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Figure 7. FIR Receive Filter Response Figure 8. FIR Receive Filter Passband Ripple For Figures 7–10, all filter plots apply to a sample rate kHz. For Figures 11–14, all filter plots apply to a sample rate ...
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Si3050 Figure 11. IIR Receive Filter Response Figure 12. IIR Receive Filter Passband Ripple Figure 13. IIR Transmit Filter Response 16 Figure 14. IIR Transmit Filter Passband Ripple Figure 15. IIR Receive Group Delay Figure 16. IIR Transmit Group Delay ...
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VD C50 R51 R53 R55 R52 R54 SCLK SDITHRU SPI Control SDO SDI CSb SDO SDI_THRU 2 19 SDI SCLK GND 4 17 FSYNCb FSYNC VDD 5 16 PCLK PCLK VA PCM Highway 6 ...
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Si3050 Bill of Materials Component C1 C5, C6, C50, C51 C7 C8, C9 C10 2 C30, C31 3 D1, D2 Dual Diode, 225 mA, 300 V, (CMPD2004S) FB1, FB2 Q1 Q4, Q5 RV1 R1 ...
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AOUT PWM Output Figure 18 illustrates an optional circuit to support the pulse width modulation (PWM) output capability of the Si3050 for call progress monitoring purposes.To enable this mode, the INTE bit (Register 2) should be set to 0, the ...
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Si3050 Functional Description The Si3050 is an integrated direct access arrangement (DAA) providing a programmable line interface that meets global telephone line requirements. The Si3050 implements Silicon Laboratories’ proprietary ISOcap™ technology, which offers the highest level of integration by replacing ...
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Table 13. Country Specific Register Settings Register 16 Country OHS OHS2 Argentina 0 Australia 1 Austria 0 Bahrain 0 Belgium 0 Brazil 0 Bulgaria 0 Canada 0 Chile 0 China 0 Colombia 0 Croatia 0 Cyprus 0 0 Czech Republic ...
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Si3050 Table 13. Country Specific Register Settings (Continued) Register 16 Country OHS Lebanon 0 Luxembourg 0 Macao 0 1 Malaysia 0 Malta 0 Mexico 0 Morocco 0 Netherlands 0 New Zealand 0 Nigeria 0 Norway 0 Oman 0 Pakistan 0 ...
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Power Supplies The Si3050 operates from a 3.0–3.6 V power supply. The Si3050 input pins can only accept 3.3 V CMOS signal levels. If support signal levels is necessary, a level shifter is required. The Si3018/19 derives ...
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Si3050 RCALD bit (Register 25, bit 5). calibration is also performed to remove offsets that might be present in the on-chip A/D converter, which could affect the A/D dynamic range. The ADC auto-calibration is initiated after the DAA dc termination ...
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Silicon Laboratories recommends that the transmit signal lower than normal transmit levels. A lower level eliminates clipping from the dc offset that results from disabling the hybrid ...
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Si3050 available with the Si3019 monitors voltage both on and off-hook. These registers can be used to help determine the following line conditions: ! When on-hook, detect if a line is connected. ! When on-hook, detect if a parallel phone ...
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Loop Current Measurement When the Si3050 is off-hook, the LCS[4:0] bits measure loop current in 3.3 mA/bit resolution. With the LCS[4:0] bits, a user can detect another phone going off-hook by monitoring the dc loop current. The line current sense ...
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Si3050 VD TGDb -24V R105 Opto-Isolator VD R104 R102 R103 RL1 TGDEb RGb 4 5 Opto-Relay Figure 20. Typical Application Circuit ...
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DC Termination The DAA has programmable settings for the dc impedance, current limiting, minimum operational loop current and TIP/RING voltage. The dc impedance of the DAA is normally represented with a 50 Ω slope as shown in Figure 21, but ...
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Si3050 impedance network for trunks. The last ac termination selection, ACIM[3:0] = 1111, is designed to satisfy minimum return loss requirements for every country that requires a complex termination. By selecting this setting, the system is ensured to meet minimum ...
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DTX. The waveform on DTX depends on the state of the RFWE bit. When RFWE is 0, DTX is –32768 ...
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Si3050 enable satisfaction of global requirements. Thresholds are set so that a ring signal is guaranteed to not be detected below the minimum, and a ring signal is guaranteed to be detected above the maximum. Pulse Dialing and Spark Quenching ...
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Billing Tone Filter (Optional) To operate without degradation during billing tones in Germany, Switzerland, and South Africa, an external LC notch filter is required. The Si3018/19 can remain off-hook during a billing tone event, but line data is lost in ...
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Si3050 off-hook, use the following procedure (also see Figure 24): 1. The Caller Alert Signal (CAS) tone is sent from the central office (CO) and is digitized along with the line data. The host processor detects the presence of this ...
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Overload Detection The Si3050 can be programmed to detect an overload condition that exceeds the normal operating power range of the DAA circuit. To use the overload detection feature, the following steps should be followed: 1. Set the OH bit ...
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Si3050 Transhybrid Balance The Si3050 contains an on-chip analog hybrid that performs the 2- to 4-wire conversion and near-end echo cancellation. This hybrid circuit is adjusted for each ac termination setting selected to achieve a minimum transhybrid balance of 20 ...
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Table 20. PCM or GCI Highway Mode Selection SCLK SDI Mode Selected Channel used Channel used Note: Values shown are the states of the pins at the rising edge of RESET. Table ...
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Si3050 PCLK FSYNC PCLK_CNT DRX MSB DTX HI-Z MSB Figure 28. PCM Highway Transmission, Short FSYNC, Single Clock Cycle Delayed Transmission ...
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PCLK FSYNC PCLK_CNT DRX DTX HI-Z Figure 30. PCM Highway Transmission, Long FSYNC, Delayed Data Transfer PCLK FSYNC PCLK_CNT DRX M SB DTX HI Figure 31. PCM Highway Double Clocked Transmission, ...
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Si3050 Companding in PCM Mode µ-Law The Si3050 supports both companding formats in addition to 16-bit linear data. The 8-bit companding schemes follow a segmented curve formatted as a sign bit, three chord bits, and four step bits. µ-Law is ...
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Table 22. µ-Law Encode-Decode Characteristics Segment #Intervals x Interval Size Number 256 128 ...
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Si3050 Table 23. A-Law Encode-Decode Characteristics Segment #intervals x interval size Number 128 ...
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SPI Control Interface The control interface to the Si3050 is a 4-wire interface modeled on commonly available micro-controller and serial peripheral devices. The interface consists of four pins: clock (SCLK), chip select (CS), serial data input (SDI), and serial data ...
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Si3050 SDO SCLK CPU CS SDI Figure 34. SPI Daisy Chain Control Architecture 44 SCLK SDI CS Si3050 #1 Channel 0 SDO SDITHRU SCLK SDI CS Si3050 #2 Channel 1 SDO SDITHRU SCLK SDI CS Si3050 #16 Channel 15 SDO ...
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BRCT 0 SDI0 0 SDI1 0 SDI2 0 SDI3 0 SDI14 0 SDI15 Figure 35. Sample SPI Control Byte to Access Channel 0 1 SDI0-15 Figure 36. Sample SPI Control Byte for Broadcast Mode (Write Only) In Figure 35 the ...
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Si3050 CSB SCLK SDI CONTROL SDO Figure 38. Read Operation via an 8-bit SPI Port Figure 37 and Figure 38 illustrate WRITE and READ operations via an 8-bit SPI controller. Each of these operations are performed as a 3-byte transfer. ...
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GCI Highway The Si3050 contains an alternate communication interface to the SPI and PCM highway control and data interface. The general circuit interface (GCI) can be used for the transmission and reception of control and data information onto a GCI ...
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Si3050 monitor channel requires manipulation of the MR and MX handshaking bits, located in bits 1 and 0 of the SC channel described below. For purposes of this specification, “downstream” is identified to be the data sent by a host ...
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The Idle state is achieved by the MX and MR bits being held inactive (signal is high) for two or more frames. When a transmission is initiated by a host device, an active state (signal is low) is present on ...
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Si3050 Idle 1st Byte Received Byte Valid New Byte Figure 43. Si3050 Monitor Receiver State Diagram ...
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MR x MXR MR x MXR Wait Idle RQT MR x RQT 1s t Byte EOM RQT nth Byte MR ack ...
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Si3050 52 Rev. 1.0 ...
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Rev. 1.0 Si3050 53 ...
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Si3050 Summary of Monitor Channel Commands Communication with the Si3050 should be in the following format: Byte 1: Device Address Byte Byte 2: Command Byte Byte 3: Register Address Byte Bytes 4-n: Data Bytes Bytes n+1, n+2: EOM Device Address ...
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Receive SC Channel : MSB 7 6 CIR6 CIR5 CIR4 These bits are defined as follows: CIR6: Reserved CIR5: Reserved CIR4: ONHM CIR3: TGDE CIR2: RG CIR1: OH Data that is received must be consistent and match for at least ...
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Si3050 Receive New CI Code = P? No Store in S Receive New C/I Code = Figure 47. Protocol for Receiving C/I Bits in the Si3050 Transmit SC Channel The following diagram shows the definition ...
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Control Registers Note: Registers not listed here are reserved and must not be written. Register Name 1 Control 1 2 Control 2 3 Interrupt Mask 4 Interrupt Source 5 DAA Control 1 6 DAA Control 2 7 Sample Rate 8 ...
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Si3050 Register 1. Control 1 Bit Name SR PWMM[1:0] Type R/W R/W Reset settings = 0000_0000 Bit Name 7 SR Software Reset Enables the DAA for normal operation Sets all registers to their ...
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Register 2. Control 2 Bit Name INTE INTP Type R/W R/W Reset settings = 0000_0011 Bit Name 7 INTE Interrupt Pin Enable The AOUT/INT pin functions as an analog output for call progress monitoring purposes. ...
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Si3050 Register 3. Interrupt Mask Bit Name RDTM ROVM FDTM BTDM DODM LCSOM TGDM POLM Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 RDTM Ring Detect Mask ring signal does not ...
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Register 4. Interrupt Source Bit Name RDTI ROVI FDTI Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 RDTI Ring Detect Interrupt ring signal is not occurring ring signal ...
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Si3050 Bit Name 1 TGDI TIP Ground Detect Interrupt. This bit is reverse logic as compared to the TGD bit The CO has not grounded TIP causing current to flow The CO has grounded TIP, causing ...
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Register 5. DAA Control 1 Bit Name RDTN RDTP Type R R Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6 RDTN Ring Detect Signal Negative negative ring signal is occurring. ...
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Si3050 Register 6. DAA Control 2 Bit Name PDL Type R/W Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4 PDL Powerdown Line-Side Device Normal operation. Program the clock generator before clearing ...
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Register 8. Reserved Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 Reserved Read returns zero. Register 9. Reserved Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 Reserved Read ...
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Si3050 Register 11. System-Side and Line-Side Device Revision Bit Name LSID[3:0] Type R Reset settings = xxxx_xxxx Bit Name 7:4 LSID[3:0] Line-Side ID Bits. These four bits will always read one of the following values, depending ...
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Register 13. Line-Side Device Revision Bit Name 1 REVB[3:0] Type R Reset settings = xxxx_xxxx Bit Name 7 Reserved Read returns zero. 6 Reserved This bit always reads a one. 5:2 REVB[3:0] Line-Side Device Revision. Four-bit ...
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Si3050 Register 15. Transmit/Receive Gain Control 1 Bit Name TXM Type R/W Reset settings = 0000_0000 Bit Name 7 TXM Transmit Mute Transmit signal is not muted Mutes the transmit signal. 6:4 ...
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Register 16. International Control 1 Bit Name OHS IIRE Type R/W R/W Reset settings = 0000_0000 Bit Name 7 Reserved This bit may be written to a zero or one. 6 OHS On-Hook Speed. This bit, ...
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Si3050 Register 17. International Control 2 Bit Name CALZ MCAL CALD RT2 Type R/W R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 CALZ Clear ADC Calibration Normal operation Clears the ...
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Register 18. International Control 3 Bit Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 Reserved This bit may be written to a zero or one. 1 RFWE Ring Detector Full-Wave Rectifier ...
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Si3050 Register 19. International Control 4 Bit Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 OVL Receive Overload Detect. This bit has the same function as ROV (Register 17), but ...
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Register 20. Call Progress Receive Attenuation Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 ARM[7:0] AOUT Receive Path Attenuation. When decremented from the default setting, these bits linearly attenuate the AOUT receive path signal used ...
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Si3050 Register 21. Call Progress Transmit Attenuation Bit Name Type Reset settings = 0000_0000 Bit Name 7:0 ATM[7:0] AOUT Transmit Path Attenuation. When decremented from the default settings, these bits linearly attenuate the AOUT trans- mit ...
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Register 22. Ring Validation Control 1 Bit Name RDLY[1:0] Type R/W Reset settings = 1001_0110 Bit Name Ring Delay Bits 1 and 0. 7:6 RDLY[1:0] These bits, in combination with the RDLY[2] bit (Register 23), set ...
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Si3050 Register 23. Ring Validation Control 2 Bit Name RDLY[2] RTO[3:0] Type R/W R/W Reset settings = 0010_1101 Bit Name 7 RDLY[2] Ring Delay Bit 2. This bit, in combination with the RDLY[1:0] bits (Register 22), sets ...
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Register 24. Ring Validation Control 3 Bit Name RNGV Type R/W Reset settings = 0001_1001 Bit Name 7 RNGV Ring Validation Enable Ring validation feature is disabled Ring validation feature is enabled in ...
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Si3050 Register 26. DC Termination Control Bit Name DCV[1:0] MINI[1:0] Type R/W R/W Reset settings = 0000_0000 Bit Name TIP/RING Voltage Adjust. 7:6 DCV[1:0] These bits adjust the voltage on the DCT pin of the line-side device, ...
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Register 27. Reserved Bit Name Type Reset settings = xxxx_xxxx Bit Name 7:0 Reserved Do not write to these register bits. Register 28. Loop Current Status Bit Name Type Reset settings = 0000_0000 Bit ...
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Si3050 Register 30. AC Termination Control Bit Name Type Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 4:5 Reserved This bit may be written to a zero or one. 3:0 ACIM[3:0] AC Impedance Selection. ...
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Register 31. DAA Control 5 Bit Name FULL FOH[1:0] Type R/W RW Reset settings = 0010_0000 Bit Name 7 FULL Full Scale Transmit and Receive Mode Default Transmit/receive full scale. This bit changes ...
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Si3050 Register 32. Ground Start Control Bit Name Type Reset settings = 0000_0x11 Bit Name 7:3 Reserved Read returns zero. 2 TGD TIP Ground Detect The CO has grounded TIP, causing current to ...
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Register 33. PCM/SPI Mode Select Bit Name PCML SPIM PCME Type R/W R/W R/W Reset settings = 0000_0000 Bit Name PCM Analog Loopback. 7 PCML 0 = Normal operation Enables analog data to be received ...
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Si3050 Register 34. PCM Transmit Start Count—Low Byte Bit Name TXS[7:0] Type Reset settings = 0000_0000 Bit Name 7:0 TXS[7:0] PCM Transmit Start Count. PCM Transmit Start Count equals the number of PCLKs following FSYNC before ...
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Register 37. PCM Receive Start Count—High Byte Bit Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1:0 RXS[9:8] PCM Receive Start Count. PCM Receive Start Count equals the number of PCLKs ...
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Si3050 Register 39. Receive Gain Control 2 Bit Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 RGA2 Receive Gain or Attenuation Incrementing the RXG2[3:0] bits results in gaining ...
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Register 40. Transmit Gain Control 3 Bit Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 TGA3 Transmit Gain or Attenuation Incrementing the TGA3[3:0] bits results in gaining up ...
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Si3050 Register 41. Receive Gain Control 3 Bit Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 RGA3 Receive Gain or Attenuation Incrementing the RXG3[3:0] bits results in gaining ...
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Register 42. GCI Control Bit Name Type Reset settings = 0000_0000 Bit Name 7:4 Reserved Read returns zero. 3:2 GCIF[1:0] GCI Data Format A-Law µ -Law 8-bit linear. The top ...
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Si3050 Register 43. Line Current/Voltage Interrupt Threshold (Si3019 line-side only) Bit Name CVT[7:0] Type Reset settings = 0000_0000 Bit Name 7:0 CVT[7:0] Current/Voltage Threshold. These bits determine the threshold at which an interrupt is generated from ...
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Register 45. Programmable Hybrid Register 1 Bit Name HYB1[7:0] Type Reset settings = 0000_0000 Bit Name 7:0 HYB1[7:0] Programmable Hybrid Register 1. These bits can be programmed with a coefficient value to adjust the hybrid response ...
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Si3050 Register 47. Programmable Hybrid Register 3 Bit Name HYB3[7:0] Type Reset settings = 0000_0000 Bit Name 7:0 HYB3[7:0] Programmable Hybrid Register 3. These bits can be programmed with a coefficient value to adjust the hybrid ...
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Register 49. Programmable Hybrid Register 5 Bit Name HYB5[7:0] Type Reset settings = 0000_0000 Bit Name 7:0 HYB5[7:0] Programmable Hybrid Register 5. These bits can be programmed with a coefficient value to adjust the hybrid response ...
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Si3050 Register 51. Programmable Hybrid Register 7 Bit Name HYB7[7:0] Type Reset settings = 0000_0000 Bit Name 7:0 HYB7[7:0] Programmable Hybrid Register 7. These bits can be programmed with a coefficient value to adjust the hybrid ...
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Register 53. Reserved Bit Name Type Reset settings = xxxx_xxxx Bit Name 7:0 Reserved Do not write to these register bits. Register 54. Reserved Bit Name Type Reset settings = xxxx_xxxx Bit Name 7:0 ...
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Si3050 Register 56. Reserved Bit Name Type Reset settings = xxxx_xxxx Bit Name 7:0 Reserved Do not write to these register bits. Register 57. Reserved Bit Name Type Reset settings = xxxx_xxxx Bit Name ...
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Register 59. Spark Quenching Control Bit Name 0 SQ1 Type R/W Reset settings = xxxx_xxxx Bit Name 7 Reserved Always write this bit to zero. Spark Quenching SQ[1:0] These bits, in combination with the OHS ...
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Si3050 A — UL 1950 Introduction Although designs using the Si3018 and Si3019 comply with UL1950 3rd Edition and pass all overcurrent and overvoltage tests, there are still several issues to consider. ...
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Pin Descriptions: Si3050 Pin # Pin Name 1 SDO Serial Port Data Output. Serial port control data output. 2 SDI Serial Port Data Input. Serial port control data input Chip Select Input. An active low input control signal ...
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Si3050 Table 26. Si3050 Pin Descriptions (Continued) Pin # Pin Name 11 TGD TIP Ground Detect Input. Used to detect current flowing in TIP for supporting ground start applications. 12 TGDE TIP Ground Detect Enable Output. Control signal for the ...
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Pin Descriptions: Si3018/19 Pin # Pin Name 1 QE Transistor Emitter. Connects to the emitter of Q3. 2 DCT DC Termination. Provides dc termination to the telephone network Receive Input. Serves as the receive side input from the ...
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Si3050 Pin # Pin Name 14 DCT3 DC Termination 3. Provides dc termination to the telephone network. 15 IGND Isolated Ground. Connects to ground on the line-side interface. 16 DCT2 DC Termination 2. Provides dc termination to the telephone network. ...
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Ordering Guide Chipset Region Si3050/19 Enhanced Global PCM/SPI or GCI Si3050/18 Global PCM/SPI or GCI Si3056/18 Global DSP Serial I/F Si3056/19 Enhanced Global DSP Serial I/F Digital Line Interface (SOIC) (SOIC) Si3019-KS Si3050-KT Si3019-KT Si3018-KS Si3050-KT Si3018-KT Si3056-KS Si3018-KS Si3056-KS ...
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Si3050 Package Outline: 20-Pin TSSOP Figure 49 illustrates the package details for the Si3050. Table 27 lists the values for the dimensions shown in the illustration. D γ Figure 49. 20-Pin Thin Shrink Small Outline Package (TSSOP) Table 27. Package ...
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Package Outline: 16-Pin TSSOP Figure 50 illustrates the package details for the Si3019. Table 28 lists the values for the dimensions shown in the illustration. D γ Figure 50. 16-Pin Thin Shrink Small Outline Package (TSSOP) Table 28. Package Diagram ...
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Si3050 Package Outline: 16-Pin SOIC Figure 51 illustrates the package details for the Si3018. Table 29 lists the values for the dimensions shown in the illustration Seating Plane Figure 51. 16-pin Small Outline ...
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Silicon Labs Si3050 Support Documentation ! AN16: Multiple Device Support ! AN17: Designing for International Safety Compliance ! AN30: Ground Start Implementation with Silicon Laboratories’ DAAs ! AN67: Layout Guidelines ! AN72: Ring Detection/Validation with the Si305x DAAs ! AN77: ...
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Si3050 Document Change List Revision 0.81 to Revision 1.0 ! Table 3 on page 7 Power Supply Current values updated. " Total Supply Current values updated. " AOUT Low Level Current added. " AOUT High Level Current added. " Note ...
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Notes: Rev. 1.0 Si3050 109 ...
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