SI3216PPQ1-EVB Silicon Laboratories Inc, SI3216PPQ1-EVB Datasheet - Page 110
SI3216PPQ1-EVB
Manufacturer Part Number
SI3216PPQ1-EVB
Description
BOARD EVAL W/SI3201 INTERFACE
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Datasheets
1.SI3216-C-FT.pdf
(122 pages)
2.SI3216PPQX-EVB.pdf
(40 pages)
3.SI3216PPQ1-EVB.pdf
(122 pages)
Specifications of SI3216PPQ1-EVB
Main Purpose
Interface, Analog Front End (AFE)
Utilized Ic / Part
Si3216
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Si3216
5. Pin Descriptions: Si3216
110
Pin #
QFN
35
36
37
38
1
2
3
4
TSSOP
Pin #
2
4
1
3
5
6
7
8
SRINGDC
STIPDC
FSYNC
RESET
QGND
FSYNC
RESET
SDCH
CAPM
SDCL
CAPP
Name
SDCH
PCLK
V
DRX
IREF
DTX
DTX
INT
CS
DDA1
10
11
12 13
1
2
3
4
5
6
7
8
9
38
Chip Select.
Active low. When inactive, SCLK and SDI are ignored and SDO is high-impedance.
When active, the serial port is operational.
Interrupt.
Maskable interrupt output. Open drain output for wire-ORed operation.
PCM Bus Clock.
Clock input for PCM bus timing.
Receive PCM Data.
Input data from PCM bus.
Transmit PCM Data.
Output data to PCM bus.
Frame Synch.
8 kHz frame synchronization signal for the PCM bus. May be short or long pulse for-
mat.
Reset.
Active low input. Hardware reset used to place all control registers in the default
state.
DC Monitor.
DC-DC converter monitor input used to detect overcurrent situations in the con-
verter.
14
37
15 16 17 18 19
QFN
36
35
34 33 32
31
30
29
28
27
26
25
24
23
22
21
20
Preliminary Rev. 0.91
SDITHRU
DCDRV
ITIPN
IRINGP
IGMP
DCFF
TEST
GNDD
VDDD
ITIPP
V
IRINGN
DDA2
Description
SRINGDC
SRINGE
STIPDC
FSYNC
RESET
SVBAT
QGND
CAPM
STIPE
SDCH
CAPP
SDCL
PCLK
V
IREF
DRX
DTX
DDA1
INT
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
TSSOP
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
SCLK
SDO
DCDRV
DCFF
IGMP
IGMN
STIPAC
SDI
SDITHRU
TEST
GNDD
VDDD
ITIPN
ITIPP
V
IRINGP
IRINGN
GNDA
SRINGAC
DDA2
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