SI3215PPQX-EVB Silicon Laboratories Inc, SI3215PPQX-EVB Datasheet - Page 100

• Manufacturer Part Number: SI3215PPQX-EVB
• Description: BOARD EVAL SI3215 QFN DISCRETE
• Manufacturer: Silicon Laboratories Inc
• Series: ProSLIC®r

Specifications of SI3215PPQX-EVB

• Main Purpose: Interface, Analog Front End (AFE)
• Utilized Ic / Part: SI3215PPQX
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1288

Si3215
Register 108. Enhancement Enable
Reset settings = 0000_0000
100
Name
Type
Bit
4:3
Bit
7
6
5
2
1
0
ILIMEN
Reserved
HYSTEN
ILIMEN
FSKEN
R/W
DCFIL
Name
DCSU
LCVE
D7
FSKEN
R/W
D6
Current Limit Increase.
When enabled, this bit temporarily increases the maximum differential current limit at the
end of a ring burst to enable a faster settling time to a dc linefeed state.
0 = The value programmed in ILIM (direct Register 71) is used.
1 = The maximum differential loop current limit is temporarily increased to 41 mA.
FSK Generation Enhancement.
When enabled, this bit will increase the clocking rate of tone generator 1 to 24 kHz only
when the REL bit (direct Register 32, bit 6) is set. Also, dedicated oscillator registers are
used for FSK generation (indirect registers 69–74). Audio tones are generated using this
new higher frequency, and oscillator 1 active and inactive timers have a finer bit resolu-
tion of 41.67 µs. This provides greater resolution during FSK caller ID signal generation.
0 = Tone generator always clocked at 8 kHz; OSC1, OSC1X., and OSC1Y are always
used.
1 = Tone generator module clocked at 24 kHz and dedicated FSK registers used only
when REL = 1; otherwise clocked at 8 kHz.
DC-DC Converter Control Speedup.
When enabled, this bit invokes a multi-threshold error control algorithm which allows the
dc-dc converter to adjust more quickly to voltage changes.
0 = Normal control algorithm used.
1 = Multi-threshold error control algorithm used.
Read returns zero.
Voltage-Based Loop Closure.
Enables loop closure to be determined by the TIP-to-RING voltage rather than loop cur-
rent.
0 = Loop closure determined by loop current.
1 = Loop closure determined by TIP-to-RING voltage.
DC-DC Converter Squelch.
When enabled, this bit squelches noise in the audio band from the dc-dc converter con-
trol loop.
0 = Voice band squelch disabled.
1 = Voice band squelch enabled.
Loop Closure Hysteresis Enable.
When enabled, this bit allows hysteresis to the loop closure calculation. The upper and
lower hysteresis thresholds are defined by indirect registers 15 and 66, respectively.
0 = Loop closure hysteresis disabled.
1 = Loop closure hysteresis enabled.
DCSU
R/W
D5
D4
Rev. 0.92
D3
Function
LCVE
R/W
D2
DCFIL
R/W
D1
HYSTEN
R/W
D0