SI3000SSI-EVB Silicon Laboratories Inc, SI3000SSI-EVB Datasheet - Page 3

• Manufacturer Part Number: SI3000SSI-EVB
• Description: BOARD EVAL PARALLEL PORT SI3000
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3000SSI-EVB

• Main Purpose: Audio, CODEC
• Utilized Ic / Part: SI3000
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Several additional signals are required for proper
operation of the serial interface. As mentioned in the
clock generation section, an MCLK must be provided for
the Si3000 to operate.
FSYNC, SCLK, SDI and SDO are also required signals
to
sychronization for the audio samples. This signal
operates at the sample rate. A high to low transition
marks the beginning of a new frame.
SCLK is an output of the Si3000 providing the bit clock
for the audio samples. Data is valid on the falling edge
of SCLK following a FSYNC start transition. SDI is audio
samples to be transmitted and SDO is audio samples
received.
The serial port signals are also used during a secondary
frame to read and write the internal registers of the
Si3000. Refer to the Si3000 data sheet for more details
on internal registers and how to read and write those
registers.
When using the board in stand-alone mode (single), set
the motherboard switches as follows: SW2 = 1 and
SW3 = 1. Figure 1 shows a typical configuration in
stand-alone mode.
Daisy-Chain Operation
The Si3000 supports an additional serial mode which
places the device in a slave mode. This serial mode is
accomplished by M1 = V
The Si3000SSI-EVB can essentially be used in two
modes: stand-alone (single) and slave. Table 2 shows
the configurations necessary for each mode.
To DSP
operate
Figure 1. Stand-Alone Connections
1
2
SW2
SW3
JP4
JP5
the
JP6
2
1
M1
Si3000.
OSC
D
JP3
M0
and M0 = GND.
Y1
FSYNC
RJ11
provides
V
V
A
D
Phone
Line
Preliminary Rev. 0.7
Power
Supply
the
In addition to JP1 and JP2 (which control the serial
mode of the local Si3000), SW2 and SW3 are used to
route the digital signals to ensure proper connection.
The SI3000SSI-EVB can be connected as a slave
through JP6. Figure 2 shows the connection of a
Si3034SSI-EVB as a master in daisy-chain mode. See
the Si3034SSI-EVB data sheet for more details.
The DSP or ASIC target system connects directly to the
master board. Only the master board needs a
connection to a power supply. V
and JP6.
When the Si3000SSI-EVB is used as a slave board, the
serial mode must be M1 = V
to configure SW2 and SW3 appropriately according to
Table 2.
Line Connection
The Si3000SSI-EVB has two physical interfaces
designed to connect to the phone line. One of the
connectors is on the motherboard (Figure 8), J1 pins 3
To DSP
Configuration
Single
Slave
Figure 2. Daisy-Chain Connections
Table 2: Si3000SSI-EVB Modes
1
2
1
2
SW2
SW3
SW2
SW3
JP4
JP4
JP5
JP5
JP6
2
JP6
1
2
1
Speaker
Master Board
SW2
M1
M1
1
2
Si3000SSI-EVB
OSC
Slave Board
JP3
M0
M0
Mic
RJ11
Y1
SW3
D
Hdst Select
Line
1
2
and M0 = GND. Be sure
In
D
is routed through JP5
RJ11
Line
Out
GND
RJ11
M1
V
D
RJ11
V
V
A
D
To
Modem
GND
Power
Supply
M0
X
3