SI3211PPTX-EVB Silicon Laboratories Inc, SI3211PPTX-EVB Datasheet - Page 14
![no-image](/images/manufacturer_photos/0/6/609/silicon_laboratories_inc_sml.jpg)
SI3211PPTX-EVB
Manufacturer Part Number
SI3211PPTX-EVB
Description
BOARD EVAL W/DISCRETE INTERFACE
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Specifications of SI3211PPTX-EVB
Main Purpose
Interface, Analog Front End (AFE)
Utilized Ic / Part
Si3211
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Table 11. Switching Characteristics—PCM Highway Serial Interface
V
Si3210/Si3211
14
PCLK Frequency
PCLK Duty Cycle Tolerance
PCLK-to-FSYNC Jitter Tolerance
Rise Time, PCLK
Fall Time, PCLK
Delay Time, PCLK Rise to DTX Active
Delay Time, PCLK Rise to DTX
Transition
Delay Time, PCLK Rise to DTX Tri-state
Setup Time, FSYNC to PCLK Fall
Hold Time, FSYNC to PCLK Fall
Setup Time, DRX to PCLK Fall
Hold Time, DRX to PCLK Fall
Notes:
D
= 3.13 to 5.25 V, T
1. All timing is referenced to the 50% level of the waveform. Input test levels are V
2. Not a valid PCLK frequency for GCI mode.
3. Specification applies to PCLK fall to DTX tri-state when that mode is selected (TRI = 0).
SCLK
SDO
Parameter
SDI
CS
A
= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, C
t
su1
t
d1
t
r
Figure 7. SPI Timing Diagram
3
Symbol
t
t
t
1/t
t
jitter
t
t
t
t
t
su1
su2
dty
t
d1
d2
d3
h1
h2
t
r
f
c
Rev. 1.5
t
su2
t
t
c
thru
Conditions
t
d2
t
Test
h2
L
= 20 pF
Min
–120
40
25
20
25
20
—
—
—
—
—
—
—
—
—
—
—
—
—
1
IH –
t
V
r
I/O –
t
h1
0.768
1.536
Typ
0.256
0.512
1.024
2.048
4.096
8.192
50
—
—
—
—
—
—
—
—
—
—
0.4V, V
1
2
2
t
cs
IL
t
d3
= 0.4 V.
Max
120
—
—
—
—
—
—
—
—
60
25
25
20
20
20
—
—
—
—
1
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
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