SI3232PPT0-EVB Silicon Laboratories Inc, SI3232PPT0-EVB Datasheet - Page 13
SI3232PPT0-EVB
Manufacturer Part Number
SI3232PPT0-EVB
Description
BOARD EVAL W/SI3200 INTERFACE
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Datasheet
1.SI3232-FQ.pdf
(128 pages)
Specifications of SI3232PPT0-EVB
Main Purpose
Interface, Analog Front End (AFE)
Utilized Ic / Part
Si3232
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Table 10. Switching Characteristics—SPI
(V
Parameter
Cycle Time SCLK
Rise Time, SCLK
Fall Time, SCLK
Delay Time, SCLK Fall to SDO
Transition
Delay Time, CS Rise to SDO Tristate
Setup Time, CS to SCLK Rise
Hold Time, SCLK Rise to CS Rise
Setup Time, SDI to SCLK Rise
Hold Time, SCLK Rise to SDI Rise
SDI to SDITHRU Propagation Delay
Note: All timing is referenced to the 50% level of the waveform. Input test levels are V
DD
, V
DD1
–V
SCLK
DD4
SDO
SDI
CS
=
3.13 to 3.47 V, T
A
=
t
0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, C
r
t
su1
Figure 1. SPI Timing Diagram
Symbol
t
t
t
t
t
t
su1
su2
t
t
d2
d3
h1
h2
t
Preliminary Rev. 0.96
c
r
f
t
su2
t
c
Conditions
t
d2
t
Test
h2
0.062
Min
15
20
25
20
—
—
—
—
—
IH
t
r
– V
t
h1
L
DD
Typ
=
—
—
—
—
—
—
—
—
—
6
–0.4 V, V
20 pF)
t
d3
IL
Max
25
25
20
20
=
—
—
—
—
—
—
Si3232
0.4 V
Unit
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
13
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