LVDS47/48EVK National Semiconductor, LVDS47/48EVK Datasheet
LVDS47/48EVK
Specifications of LVDS47/48EVK
*LVDS47/48EVK/NOPB
LVDS47/48EVK/NOPB
Related parts for LVDS47/48EVK
LVDS47/48EVK Summary of contents
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... LVDS Flow Through Evaluation Boards LVDS47/48EVK Revision 1.0 January 2000 ...
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... RJ45 cable. Probe points for a separate driver and a separate receiver are also provided for individual line driver or receiver testing. The part number for the Evaluation kit is LVDS47/48EVK. In this application note, the following differential signal nomenclature has been used: “Jx-3” represents the true signal and “Jx-1” represents the inverting signal. On the PCB, the true signal is represented by a ‘ ...
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Five Test Cases Five different test cases are provided on this simple 4 layer FR-4 PCB. Each case is described separately. The five test cases are shown in Figure 1. LVDS Channel # 1A: LVDS Line Driver This test ...
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J3 V GND Driver 50 RT1 J4 V GND 50 CC RT5 100 Receiver RT5/ RT6 J3 V GND Driver 50 RT2 J3 V GND CC EN I3/I4 ...
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Interconnecting Cable and Connector The evaluation PCB has been designed to directly accommodate a CAT 5 four twisted pair (8-pin) RJ45 cable. The pinout, connector, and cable electrical/mechanical characteristics are defined in the Ethernet standard and the cable is ...
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LVDS signals should be kept away from CMOS logic signals to minimize noise coupling from the large swing CMOS signals. This has been accomplished on the PCB by routing CMOS signals on a different signal layer (bottom) than the LVDS ...
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The PCB interconnect signal (LVDS Channel #2) can be measured at the receiver inputs (test points J6-1 and J6-3). Due to the short interconnect path via the PCB little distortion to the waveform is caused by the interconnect. See Figure ...
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Figure 6: LVDS Channel #3 Waveforms - 1m Cable Interconnect Figure 7: LVDS Channel #3 Waveforms - 5m Cable Interconnect ...
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Figure 8: LVDS Channel #3 Waveforms - 10m Cable Interconnect 6.1.6 Probing of High Speed LVDS Signals Probe specifications for measuring LVDS signals are unique due to the low drive level of LVDS (3 mA typical). Either a high impedance ...
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Figure 9: LVDS Channel #2 Waveforms - differential and calculated differential from single-ended waveform LVDS waveforms may also be measured with high impedance probes such as common SD14 probe heads. These probes offer 100k Ohm, 0.4 pF loading and a ...
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Option 3: Disabling the LVDS Receiver The quad receiver features a ganged enable (same as the driver). An active high or an active low are provided. On the evaluation PCB, the active low input (EN*) is routed to ground. The ...
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Figure 10: LVDS Cannel #1B Waveforms – A Small Amount of Common Mode Noise Coupled from Output to Input Figure 11: LVDS Channel #1B Waveforms – Output Disabled ...
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Summary This evaluation PCB provides a simple tool to evaluate LVDS signaling across different media and lengths to determine signal quality for high speed data transmission applications. 6.1.11 Appendix Typical test equipment used for LVDS measurements: Signal Generator TEK ...
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... LVDS Flow Through Evaluation Boards LVDS47/48EVK Revision 1.0 January 2000 ...
Page 15
... RJ45 cable. Probe points for a separate driver and a separate receiver are also provided for individual line driver or receiver testing. The part number for the Evaluation kit is LVDS47/48EVK. In this application note, the following differential signal nomenclature has been used: “Jx-3” represents the true signal and “Jx-1” represents the inverting signal. On the PCB, the true signal is represented by a ‘ ...
Page 16
Five Test Cases Five different test cases are provided on this simple 4 layer FR-4 PCB. Each case is described separately. The five test cases are shown in Figure 1. LVDS Channel # 1A: LVDS Line Driver This test ...
Page 17
J3 V GND Driver 50 RT1 J4 V GND 50 CC RT5 100 Receiver RT5/ RT6 J3 V GND Driver 50 RT2 J3 V GND CC EN I3/I4 ...
Page 18
Interconnecting Cable and Connector The evaluation PCB has been designed to directly accommodate a CAT 5 four twisted pair (8-pin) RJ45 cable. The pinout, connector, and cable electrical/mechanical characteristics are defined in the Ethernet standard and the cable is ...
Page 19
LVDS signals should be kept away from CMOS logic signals to minimize noise coupling from the large swing CMOS signals. This has been accomplished on the PCB by routing CMOS signals on a different signal layer (bottom) than the LVDS ...
Page 20
The PCB interconnect signal (LVDS Channel #2) can be measured at the receiver inputs (test points J6-1 and J6-3). Due to the short interconnect path via the PCB little distortion to the waveform is caused by the interconnect. See Figure ...
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Figure 6: LVDS Channel #3 Waveforms - 1m Cable Interconnect Figure 7: LVDS Channel #3 Waveforms - 5m Cable Interconnect ...
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Figure 8: LVDS Channel #3 Waveforms - 10m Cable Interconnect 6.1.6 Probing of High Speed LVDS Signals Probe specifications for measuring LVDS signals are unique due to the low drive level of LVDS (3 mA typical). Either a high impedance ...
Page 23
Figure 9: LVDS Channel #2 Waveforms - differential and calculated differential from single-ended waveform LVDS waveforms may also be measured with high impedance probes such as common SD14 probe heads. These probes offer 100k Ohm, 0.4 pF loading and a ...
Page 24
Option 3: Disabling the LVDS Receiver The quad receiver features a ganged enable (same as the driver). An active high or an active low are provided. On the evaluation PCB, the active low input (EN*) is routed to ground. The ...
Page 25
Figure 10: LVDS Cannel #1B Waveforms – A Small Amount of Common Mode Noise Coupled from Output to Input Figure 11: LVDS Channel #1B Waveforms – Output Disabled ...
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Summary This evaluation PCB provides a simple tool to evaluate LVDS signaling across different media and lengths to determine signal quality for high speed data transmission applications. 6.1.11 Appendix Typical test equipment used for LVDS measurements: Signal Generator TEK ...