ISL6142/52EVAL1 Intersil, ISL6142/52EVAL1 Datasheet - Page 3

• Manufacturer Part Number: ISL6142/52EVAL1
• Description: EVAL BOARD W/CURRENT MONITOR
• Manufacturer: Intersil

Specifications of ISL6142/52EVAL1

• Main Purpose: Power Management, Hot Swap Controller
• Utilized Ic / Part: ISL6142, 6152
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

• The evaluation platform provides the user two channels (A
• The boards can be used in a positive supply configuration,
• The default application circuit is set for a for maximum
• The typical load is a -48V to 5V brick regulator which is not
+5V
+5V
-V
-V
device at lower supply levels will produce a lower intensity
visual fault indication for the D5A/B LED
and B) for analysis which can share the same power
supply or be driven independently with different voltages.
There is no interaction between the two channels (other
than sharing the common GND), and there is no
requirement for special power up or power down
sequencing. Channel A is populated with the ISL6152 and
channel B is populated with the ISL6142, however an
additional unit of each product is supplied for analysis.
Channel “B” is designed with socketed through-hole
components to make modifications and circuit analysis
user friendly. The boards are labeled for negative supply
operation; GND is the most positive voltage, -VINA and -
VINB are the most negative voltages. Note that GND is
common for both channels on all three boards. Since most
IC signals are referenced to the negative rail, the user may
want to reference the voltmeter and oscilloscope GNDs to
the negative supply. However, be careful of earth GND
connections (on power supplies or oscilloscopes) that
don’t match the user’s GND.
as long as the user renames (mentally or physically) the
signals (GND becomes the positive supply, -VINA/-VINB
become the new GND). In this configuration both supplies
must be the same voltage.
operating voltage (Over-Voltage threshold) of -56V. A
minimum operating voltage of -44.5V is required at power-
up (increasing UV threshold) and the device will turn off
the FET when the supply drops below approximately -40V.
included on the load board. However, connector terminals
(posts) are provided at the output side of the control board
making it easy to connect to a brick regulator or modify the
load characteristics if desired.
IN
IN
SW2A
SW1B
(DIS)
(DIS)
SW2B
(UV)
(UV)
SW1A
CONTROL BOARD
FIGURE 2. LEDs AND SWITCHES
D6B LED (OC FLT)
D6A LED
D5B LED
D5A LED
(PWRGD)
(PWRGD)
(OC FLT)
3
SW12A
600Ω
A ON LED
ON
OFF
SW11A
300Ω
OFF
ON
BOARD
LOAD
SW11B
600Ω
ON
OFF
B ON LED
SW12B
300Ω
OFF
ON
BUS board (Input -48V Power; Fig. 6)
• Multiple large holes for soldering wires, posts, pins, etc.
• Holes for optional input caps
• Edge connector pins plug into the Control board to
• Separate GND connector pin that can be modified (trace
CONTROL Board (IC Hot-Plug; Fig. 7)
• Two hot plug channels
• Compare Intersil ISL6142 (L) to ISL6152 (H)
• Easily change application components and evaluate
• Power good (D5A/B) and Over-Current Time-Out (D6A/B)
• Push-button Switch (SW1A/B) resets the Over-Current
• Mini toggle switch SW2 disables the external FET when
• JP1A and JP1B connect the A3 ground trace from the Bus
• Footprints for 3 FET outlines; D2PAK, SO-8, SOT-223
• Test points for most IC pins, GND (black), -VINA/B, and -
• Red test pins (+5VA/B) provided to connect the external
• Small bread-board area for adding additional circuitry
• Approximate minimum board area highlighted (ch. A)
• Footprints for load capacitors (C5A/B)
• Footprints for RC filter on V
for input power (-48V and GND typical)
simulate/evaluate hot insertions
shortened) and used to simulate last pin making contact.
JP1A and JP1B on the Control board must be removed to
enable the short pin ground configuration.
circuit performance with the socketed through hole
components of channel B
LED “FAULT” indicators. The power good fault LED
functions only for the ISL6142. Removing JP3A/3B
isolates the PWRGD/PWRGD output pin from the fault
indicator circuitry for the respective channel. Note that the
power good output pin is still connected to the
TPPGA/TPPGB test pin on the load board with the jumper
removed.
latch by temporarily shorting the UV pin to -V
switched to +5V (with respect to -V
Over-Current latch when toggled high to low. Removing
JP2A or JP2B allows the user to by-pass the SW2A/B
switch and drive the DIS pin externally.
board (short pin ground) to main ground on the Control
board. The jumper should be open if a short pin
configuration is desired.
V
+5V supply (referenced to -V
OUT
.
DD
IN
) to the Control board
(channel B only)
IN
) and resets the
IN