LM25061MM-2EVAL National Semiconductor, LM25061MM-2EVAL Datasheet - Page 5

• Manufacturer Part Number: LM25061MM-2EVAL
• Description: BOARD EVALUATION LM25061
• Manufacturer: National Semiconductor

Specifications of LM25061MM-2EVAL

• Main Purpose: Power Management, Hot Swap Controller
• Embedded: No
• Utilized Ic / Part: LM25061-2
• Primary Attributes: High Side MOSFET Driver, Inrush Current Limiting
• Secondary Attributes: Auto Restart, 2.9 V ~ 17 V Supply
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

UVLO Input Voltage Threshold
Programming the UVLO thresholds sets the minimum system
voltage to enable the series pass device (Q1). If V
the UVLO thresholds, Q1 is switched off, denying power to
the load. Programmable hysteresis is provided.
OPTION A
The UVLO thresholds are set with two resistors (R1, R2) as
shown in Figure 5.
The two resistor values are calculated as follows:
(V
Where the resistor values are known, the threshold voltages
and hysteresis are calculated from the following:
UVL
- Choose the upper and lower UVLO thresholds (V
).
FIGURE 5. Programming the UVLO Threshold
SYS
UVH
is below
) and
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5
OPTION B
The minimum UVLO level is obtained by connecting the UV-
LO pin to VIN as shown in Figure 6. On this evaluation board
the UVLO pin is accessible at the TP1 test point located to the
right of the toggle switch. Q1 is switched on when the VIN
voltage reaches the POR threshold (
Shutdown
With the circuit in normal operation, the LM25061 can be
shutdown by grounding the UVLO pin. Test point TP1, located
to the right of the toggle switch, can be used for this purpose.
POWER GOOD and FB Pins
During turn-on, the Power Good pin (PGD) is high until the
voltage at VIN increases above
low, remaining low as the input voltage increases. When the
voltage at the board’s output pin increases above 13V PGD
switches high. PGD switches low when the output voltage
decreases below 12.5V. Additionally, PGD switches low if the
UVLO pin is taken below its threshold regardless of the output
voltage.
The output voltage threshold for the PGD pin is set with two
resistors (R3, R4) at the FB pin as shown in Figure 7.
FIGURE 6. UVLO = POR
V
UV(HYS)
= R1 x 20 µA
≊
1.6V. PGD then switches
≊
2.6V).
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