SD005EVK National Semiconductor, SD005EVK Datasheet - Page 4
SD005EVK
Manufacturer Part Number
SD005EVK
Description
BOARD EVALUATION CLC005
Manufacturer
National Semiconductor
Datasheet
1.CLC005AJENOPB.pdf
(12 pages)
Specifications of SD005EVK
Design Resources
SD005EVK Schematic
Main Purpose
Interface, Digital Cable Driver
Utilized Ic / Part
CLC005
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Not Compliant
www.national.com
Operation
INPUT INTERFACING
The CLC005 has high impedance, emitter-follower buffered,
differential inputs. Single-ended signals may also be input.
Transmission lines supplying input signals must be properly
terminated close to the CLC005. Either A.C. or D.C. coupling
as in Figure 2 or Figure 3 may be used. Figures 2, 4 and Fig-
ure 5 show how Thevenin-equivalent resistor networks are
Load Type
ECL, 50 , 5V, V
ECL, 50 , 5.2V, V
ECL, 75 , 5V, V
ECL, 75 , 5.2V, V
800mV
800mV
800mV
P-P
P-P
P-P
, 50 , 5V, V
, 75 , 5V, V
, 2.2K , 5V, V
T
T
=2V
=2V
T
T
=2V
=2V
T
T
=1.6V
=1.6V
T
=1.6V
Resistor to V
FIGURE 2. AC Coupled Input
3240
82.5
80.6
75.0
124
121
110
FIGURE 1. Input Stage
CC
(R1)
4
used to provide input termination and biasing. The input D.C.
common-mode voltage range is 0.8V to 2.5V below the posi-
tive power supply (V
kept within the specified common-mode range. For an 800
mV
to 2.1V below the positive supply.
P-P
input signal, typical input bias levels range from 1.2V
Resistor to V
DS100144-4
6810
124
133
187
196
154
232
CC
EE
). Input signals plus bias should be
(R2)
DS100144-5