CYP15G0101DX-EVAL Cypress Semiconductor Corp, CYP15G0101DX-EVAL Datasheet
CYP15G0101DX-EVAL
Specifications of CYP15G0101DX-EVAL
Related parts for CYP15G0101DX-EVAL
CYP15G0101DX-EVAL Summary of contents
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... CYP15G0101DXB Evaluation Cypress Semiconductor Corporation Board User’s Guide • 3901 North First Street • San Jose , CA 95134 • 408-943-2600 August 12, 2003 [+] Feedback ...
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... Test Set-up and Result Verification ........................................................................................................................... 22 7. Schematic Diagram, PCB Layout, and Bill of Materials (BOM) ....................................................................................... 23 Appendix A. Schematic Diagram of CYP15G0101DXB Evaluation Board .......................................................................... 24 Appendix B. PCB Layout for CYP15G0101DXB Evaluation Board ..................................................................................... 30 Appendix C. Bill Of Materials (BOM) CYP15G0101DXB Evaluation Board ......................................................................... 39 CYP15G0101DXB Evaluation Board User’s Guide 2 [+] Feedback ...
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... Figure 16. Adding Two Framing Characters to Data Stream ............................................................................................... 22 Figure 17. CYP15G0101DXB-EVAL Top Level Schematics .................................................................................................. 25 Figure 18. CYP15G0101DXB-EVAL Terminated Transmitter & Receiver Blocks ............................................................... 26 Figure 19. CYP15G0101DXB-EVAL Terminated Control Signals Block .............................................................................. 27 Figure 20. CYP15G0101DXB-EVAL Transmit and Receive Clock Schematics .................................................................. 28 Figure 21. CYP15G0101DXB-EVAL Input Power Schematics .............................................................................................. 29 Figure 22. CYP15G0101DXB-EVAL Top Layout .................................................................................................................... 31 Figure 23. CYP15G0101DXB-EVAL Bottom Layout .............................................................................................................. 32 Figure 24 ...
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... List of Tables Table 1. Description of Connectors of the CYP15G0101DXB Evaluation Board ............................................................... 10 Table 2. Description of Control Pins in JT7 ........................................................................................................................... 11 Table 3. The High, Mid, and Low Levels on JT32 .................................................................................................................. 15 Table 4. The Levels of Different Static Signals on JT7 for BIST Mode ............................................................................... 16 Table 5. Channel Enabling Controls ...................................................................................................................................... 17 Table 6. The Levels of Static Signals on JT32 for Parallel In-Parallel Out Mode (Encoded) ............................................ 20 Table 7 ...
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... MBaud. This document describes the operation and interface of the CYP15G0101DXB evaluation board. The evaluation board allows users to become familiar with the functionality of the CYP15G0101DXB. Figure 4 gives a skeletal view of the evaluation board. 2. Kit Contents • ...
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... Functional Description of CYP15G0101DXB Figure 2 shows the block diagram of CYP15G0101DXB, which has a pair of transmit and receive channels. Figure 1 shows the transmitter section of CYP15G0101DXB. TRANSMIT PLL TXRATE CLOCK MULTIPLIER SPDSEL CHARACTER-RATE CLOCK TXCLKO+ TXCLKO– 2 TXMODE[1:0] TXCKSEL TXPER SCSEL TXD[7:0] 8 TXOP 2 TXCT[1: TXCLK ...
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... Figure 3 shows the receive section of the CYP15G0101DXB. The serial data input passes through the framer (where the recovered bit stream is framed to framing character), the 10B/8B Decoder and the elasticity buffer. RX-PLL Enable RXLE L BOE[7:0] CHARACTER RATE CLOCK SDASEL LPEN R ECEIVE INSEL ...
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... Board Layout, Photograph and Pin Descriptions Figure 4 shows the skeletal view of the CYP15G0101DX board. Figure 4. CYP15G0101DXB-EVAL Skeletal View CYP15G0101DXB Evaluation Board User’s Guide 8 [+] Feedback ...
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... Figure 5 shows the different connectors and pins of the evaluation board for CYP15G0101DXB. Figure 5. Pin Description of CYP15G0101DXB-EVAL CYP15G0101DXB Evaluation Board User’s Guide 9 [+] Feedback ...
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... V DC Banana Jack • Ground Indicates if the power supply is ON. The LED glows when the power supply goes ON. Note: For CYP15G0101DXB, there is no dedicated JTAG reset. The JTAG logic will be reset on power-on. LVTTL Input TXD[7:0] • Transmit Data Input • 50 Ohms Impedance terminated to 50 ohms load TXCT[1:0] • ...
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... Table 1. Description of Connectors of the CYP15G0101DXB Evaluation Board (continued) Connectors Signals JT12 REFCLK JT14 REFCLK* DT2 LFI SWT1 BOE[1:0] RXLE OELE BISTLE TRSTZ JT5 Optical Controls XT1 The optical Interface JT6 RXD[7:0] RXST[2:0] RXOP UT1 CYP15G0101DXB Table 2 gives a detailed description of all the control pins in JT7. ...
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... The elasticity buffer is bypassed. • H: Invalid State. RFMODE Reframe Mode Select. 3-Level Select Please refer to the data sheet for CYP15G0101DXB for detailed information. FRAMCHAR Framing Character Select. 3-Level select. Please refer to the data sheet for CYP15G0101DXB for detailed information. CYP15G0101DXB Evaluation Board User’s Guide ...
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... Test Modes The different test modes discussed in this document are as follows: 1. BIST mode CYP15G0101DXB has the Built-In Self-Test (BIST) capability. The transmit and receive channel contain the BIST Pattern Generator and Checker respectively. Figure 6 shows the BIST mode operation. Ext. BIST Int ...
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... External clock input is located at JT12 or JT14. For single ended REFCLK apply an LVTTL clock signal to REFCLK input in JT12 and leave REFCLK*(JT14) input floating.) Figure 8. Controlling REFCLK Settings CYP15G0101DXB Evaluation Board User’s Guide Figure 7. Control Switches for Test Set-up shunt here to ...
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... Instrument-grade power supply 1 Amp @ 3.3V • Oscilloscope (500 MHz or better) • Digital Signal Analyzer. • Multimeter Cable Needed: • SMA-to-SMA coaxial cables • Power supply cables. CYP15G0101DXB Evaluation Board User’s Guide Push this side to set LOW LOW Row MID (no shunt) HIGH Figure 10 ...
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... Input Figure 11. Pictorial Representation of the Internal BIST Set-up 6.2.1.3 Test Set-up The intention of this set- test CYP15G0101DXB in BIST mode. Follow the procedure below for the test set-up. 1. Connect the clock input to the internal clock by placing a shunt across the XTAL_OUT on JT9. 2. Configure the JT7 pins using the following settings in Table 4 by adjusting their shunt position:. ...
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... Trigger the signal analyzer by connecting a jumper-to-SMA cable from TXCLKO on JT9 to the trigger input on the analyzer. • Verify on the signal analyzer that the eye diagram looks as shown in Figure 13. Make sure that the eye width is equal to 1-bit period. CYP15G0101DXB Evaluation Board User’s Guide BIST Channel Enable (OELE) (BISTLE) OUT2± ...
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... Configure the JT32 pins using the same settings mentioned in step 2 of Section 6.2.1.3, except for the following change. Change LPEN from HIGH to LOW in Table 4. 4. Continue with all other subsequent steps in Section 6.2.1.3. Figure 14. Coaxial Cable Connection for External BIST Mode CYP15G0101DXB Evaluation Board User’s Guide 18 [+] Feedback ...
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... Parallel Data In – Parallel Data Out Mode The intention of this set- test CYP15G0101DXB in parallel-in and parallel-out mode for encoded and unencoded data. 6.3.1 Encoded Mode 6.3.1.1 Equipment Required Equipment needed: • CYP15G0101DXB evaluation board • Instrument-grade power supply 1 Amp @ 3.3V • ...
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... Retain the test set-up as described in Section 6.3.1.2 on page 19. Now make the following changes to the set-up. 1. The shunts on JT7 should be placed in the following manner. The highlighted texts show the changes made to Table 6 on page 20. CYP15G0101DXB Evaluation Board User’s Guide Signal Level ...
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... TXD[2] DIN[2] TXD[3] DIN[3] TXD[4] DIN[4] TXD[5] DIN[5] TXD[6] DIN[6] TXD[7] DIN[7] TXCT[0] DIN[8] TXCT[1] DIN[9] (MSB) CYP15G0101DXB Evaluation Board User’s Guide Signal Level SPDSEL HIGH SDASEL LOW PARCTL LOW RXMODE LOW RXCKSEL MID RFMODE MID DECMODE = MID or HIGH RXST[2] ...
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... A clock should be connected to TXCLK input and this clock must have identical frequency to REFCLK. b.Once dataflow has started, move TXRST* jumper in JT7 from HIGH to LOW and then back to HIGH. This will reset the phase align buffer to absorb the phase differences between the TxCLK and REFCLK. CYP15G0101DXB Evaluation Board User’s Guide REFCLK 17C ...
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... Schematic Diagram, PCB Layout, and Bill of Materials (BOM) Figure 17 to Figure 21 in Appendix A shows the schematic diagram of the CYP15G0101DXB-EVAL. Figure 22 to Figure 29 in Appendix B shows the PCB layout of each layer of the CYP15G0101DXB-EVAL. The Bill of Materials (BOM) of the evaluation board is listed in Appendix C in Table 11. ...
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... Appendix A. Schematic Diagram of CYP15G0101DXB Evaluation Board CYP15G0101DXB Evaluation Board User’s Guide 24 [+] Feedback ...
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... CYP15G0101DXB Evaluation Board User’s Guide Figure 17. CYP15G0101DXB-EVAL Top Level Schematics 25 [+] Feedback ...
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... CYP15G0101DXB Evaluation Board User’s Guide Figure 18. CYP15G0101DXB-EVAL Terminated Transmitter & Receiver Blocks 26 [+] Feedback ...
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... CYP15G0101DXB Evaluation Board User’s Guide Figure 19. CYP15G0101DXB-EVAL Terminated Control Signals Block 27 [+] Feedback ...
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... CYP15G0101DXB Evaluation Board User’s Guide Figure 20. CYP15G0101DXB-EVAL Transmit and Receive Clock Schematics 28 [+] Feedback ...
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... CYP15G0101DXB Evaluation Board User’s Guide Figure 21. CYP15G0101DXB-EVAL Input Power Schematics 29 [+] Feedback ...
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... CYP15G0101DXB Evaluation Board User’s Guide Appendix B. PCB Layout for CYP15G0101DXB Evaluation Board 30 [+] Feedback ...
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... CYP15G0101DXB Evaluation Board User’s Guide Figure 22. CYP15G0101DXB-EVAL Top Layout 31 [+] Feedback ...
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... CYP15G0101DXB Evaluation Board User’s Guide Figure 23. CYP15G0101DXB-EVAL Bottom Layout 32 [+] Feedback ...
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... CYP15G0101DXB Evaluation Board User’s Guide Figure 24. CYP15G0101DXB-EVAL Top Layer Silk Layout 33 [+] Feedback ...
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... CYP15G0101DXB Evaluation Board User’s Guide Figure 25. CYP15G0101DXB-EVAL Bottom Layer Silk Layout 34 [+] Feedback ...
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... CYP15G0101DXB Evaluation Board User’s Guide Figure 26. CYP15G0101DXB-EVAL Top Layer Solder Mask Layout 35 [+] Feedback ...
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... CYP15G0101DXB Evaluation Board User’s Guide Figure 27. CYP15G0101DXB-EVAL Bottom Layer Solder Mask Layout 36 [+] Feedback ...
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... CYP15G0101DXB Evaluation Board User’s Guide Figure 28. CYP15G0101DXB-EVAL Power Plane Layout 37 [+] Feedback ...
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... CYP15G0101DXB Evaluation Board User’s Guide Figure 29. CYP15G0101DXB-EVAL Ground Plane Layout 38 [+] Feedback ...
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... Appendix C. Bill Of Materials (BOM) CYP15G0101DXB Evaluation Board CYP15G0101DXB Evaluation Board User’s Guide 39 [+] Feedback ...
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... Table 11.CYP15G0101DXB Eval Board Bill Of Materials Part Name CAP-.1UF CB1,CB2,CB5, CB6,CB7,CB8, CB9,CT1,CT6, CT7,CT8,CT9, CT10,CT11 CAP-SMDC0805V-2400PF CT2,CT3,CT4, CT5 CAPPOL-10UF CB3,CB4,CB10 CLK_HCMOS-LCC197X295P4 UB1 CYP15G0101DXB_BGA100 UT1 ECONORESET_SOT23 QT1 ETHR1G_OXCVR-MSA_SFP XT1 HEADER10-HDR100STR2X5 JT11 HEADER26-HDR100STR2X13 JT5,JT6,JT9,JT10 HEADER3X18-HDR100STR JT7 SHUNT INDUCTOR-10UH LB1,LB2 JACK-BASE-CONJBANANA JT8,JT13 LED-N/A DT1,DT2 ...
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... Table 11.CYP15G0101DXB Eval Board Bill Of Materials (continued) Part Name SMA_THRU-SMA_TH_VERT JT1-JT4,JT12,JT14 SWITCH_DIP8 SWT1 ZENER-5.1V DT3 ESCON is a registered trademark of IBM. HOTLink is a registered trademark and HOTLink II and MultiFrame are trademarks of Cypress. All product and company names mentioned in this document may be the trademarks of their respective holders. ...