AD9858/TLPCBZ Analog Devices Inc, AD9858/TLPCBZ Datasheet - Page 26

• Manufacturer Part Number: AD9858/TLPCBZ
• Description: BOARD EVAL TRANSLATION LOOP
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9858/TLPCBZ

• Design Resources: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109)
• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Utilized Ic / Part: AD9858/TL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

AD9858
Profile Selection
A profile consists of a specific group of memory registers (see
Table 6). In the AD9858, each profile contains a 32-bit frequency
tuning word and a 14-bit phase offset word. Each profile is
selectable via two external profile select pins (PS0 and PS1), as
defined in Table 12. The specific mapping of registers to profiles is
detailed in the Register Bit Descriptions section. The user should
be aware that selection of a profile is internally synchronized
with DDS CLK using the SYNCLK timing. That is, SYNCLK is
used to synchronize the assertion of the profile select pins (PS0
and PS1). Therefore, the PS0 and PS1 pins must be set up and
held around the rising edge of SYNCLK.
Table 12.
PS1
0
0
1
1
PS0
0
1
0
1
Profile
0
1
2
3
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The profiles are available to the user to provide rapid changing
of device parameters via external hardware, which alleviates the
speed limitations imposed by the I/O port. For example, the user
might preprogram the four phase offset registers with values that
correspond to phase increments of 90°. By controlling the PS0 and
PS1 pins, the user can implement π /2 phase modulation. The data
modulation rate is much higher than that possible by repeatedly
reloading a single phase offset register via the I/O port.