CDB4955A Cirrus Logic Inc, CDB4955A Datasheet - Page 6

• Manufacturer Part Number: CDB4955A
• Description: EVALUATION BOARD FOR CS4955A
• Manufacturer: Cirrus Logic Inc

Specifications of CDB4955A

• Main Purpose: Video, Video Processing
• Embedded: Yes, Other
• Utilized Ic / Part: CS4955
• Primary Attributes: NTSC/PAL Digital Video Encoder
• Secondary Attributes: Graphical User Interface, RS-232 Interface
• Operating Frequency: 27 MHz
• Interface Type: RS-232, Composite, RGB, S-Video
• Operating Supply Voltage: 3.3 V, 5 V
• Software: Software Included
• Silicon Manufacturer: Cirrus Logic
• Silicon Core Number: CS4955
• Kit Application Type: Audio / Video / TV
• Application Sub Type: Encoder / Decoder
• Kit Contents: Evaluation Board
• Rohs Compliant: No
• For Use With/related Products: CS4954
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

2.2.2.2
This option selects the video source which will
serve as input for the CS4954/55. Internal Video
means all video content which is supplied by the
FPGA. External parallel inputs use J4, the 25 pin
D-Sub connector. External serial inputs use J19,
the right angle BNC connector.
2.2.2.3
This option downloads a previously converted bit-
map file to SDRAM on the evaluation board and
displays it on the video outputs. Either a NTSC or
a PAL format file may be downloaded and dis-
played, but the monitor used must be compatible
with the downloaded file format to display correct-
ly.
2.2.2.4
This option downloads and stores a previously con-
verted bitmap file to a block of on board Flash
memory. FLASH block 1 is contains the Cirrus
logo screen in NTSC format, while FLASH block
2 contains the Cirrus logo screen in PAL format.
2.2.2.5
This option displays video from one of the 3
FLASH blocks.
2.2.2.6
This option displays one of the eight test patterns
generated by the control FPGA. These patterns are
color bars, luma bars, step, aqua screen, luma ramp
(1 bit/2 pixel ramp rate), luma ramp (1bit/pixel),
luma ramp (2bits/pixel), and luma ramp (4bits/pix-
el).
3. COMMAND LINE PARAMETERS
There are two valid command line parameters
which can be used to modify the action of the pro-
gram.
6
Video Input Source Option
Download a CCIR656 File to
SDRAM and Display Option
Download a CCIR656 File to Flash
Option
Display Video from Flash Option
Display Test Patterns Option
-f: This parameter shows the FPGA Register Val-
ues tab. This allows FPGA registers to be manipu-
lated directly. Note that the FPGA Register is NOT
part of the CS4954/55.
-m: This parameter shows the Macrovision
isters tabs if a CS4955 is in place on the
CDB4954A/55A Evaluation Board. If a CS4954 is
in place on the board, the Macrovision Registers
tabs are not shown (since the CS4954 doesn’t have
Macrovision support) whether or not the "-m" com-
mand line parameter is included.
4. 3.3 V OR 5 V INTERFACE
The CS4954 allows either 3.3 V or 5 V operation. The
CDB4954A/55A evaluation board is built so that you
can test this feature by changing jumper configura-
tions. The voltage should only be changed when no
power is applied. Please refer to
5. DIGITAL VIDEO INTERFACE
The evaluation board is designed to accept the stan-
dard ITU-R BT.656 (i.e.: ECL) levels, but it also
allows for TTL levels and SMPTE-259M serial
digital interface to facilitate system development.
Please refer to
of all the connectors located on the board.
6. ANALOG OUTPUT
Before connecting equipment such as a monitor to
one of the analog video outputs, verify that the
jumper configuration for the video connectors are
properly set for your application.
7. OUTPUT FILTERS
The filters present on the evaluation board are cal-
culated for both high impedance loads (doubly ter-
minated 300 Ω) and low impedance loads (doubly
terminated 75 Ω). Please note that when in low im-
pedance mode, only 3 DACs may be enabled. Refer
to
Also, the CDB4954A/55A evaluation board allows
for other filter topologies by providing an extra op-
amp with open pads. Please refer to
more detail.
Table 2 on page 7
Table 2 on page 7
for the proper configuration.
CDB4954A/55A
Table 1 on page
for a description
Figure 9
®
Reg-
7.
for