CDB5460AU Cirrus Logic Inc, CDB5460AU Datasheet - Page 48

• Manufacturer Part Number: CDB5460AU
• Description: EVALUATION BOARD FOR CS5460A
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5460AU

• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CS5460A
• Primary Attributes: 1-Phase Current & Voltage Monitoring
• Secondary Attributes: Graphical User Interface, SPI™ & USB Interfaces
• Processor To Be Evaluated: CS5460A, C8051F320
• Interface Type: USB
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

5.9 Power Offset Register
5.10 Current Channel AC Offset Register and Voltage Channel AC Offset Register
5.11 Status Register and Mask Register
48
MSB
MSB
-(2
2
-13
0
PWOR
Address:
Default** = 0.000
This offset value is added to each power value that is computed for each voltage/current sample pair before
being accumulated in the Energy Register. The numeric format of this register is two’s complement notation.
This register can be used to offset contributions to the energy result that are caused by undesirable sources of
energy that are inherent in the system.
Address:
Default** = 0.000
The AC offset registers are initialized to zero on reset, allowing the device to function and perform measure-
ments. First, the ground-level input should be applied to the inputs. Then the AC Offset Calibration Command
is should be sent to the CS5460A. After ~(6N + 30) A/D conversion cycles (where N is the value of the Cy-
cle-Count Register), the gain register(s) is loaded with the square of the system AC offset value. DRDY will be
asserted at the end of the calibration. The register may be read and stored so the register may be restored with
the desired system offset compensation. Note that this register value represents the square of the AC cur-
rent/voltage offset.
Address:
Default** = Binary: 00000000000000xxxx000001 (Status Register)
The Status Register indicates the condition of the chip. In normal operation writing a '1' to a bit will cause the bit
to go to the '0' state. Writing a '0' to a bit will maintain the status bit in its current state. With this feature the user
can write logic ‘1’ values back to the Status Register to selectively clear only those bits that have been re-
solved/registered by the system MCU, without concern of clearing any newly set bits. Even if a status bit is
masked to prevent the interrupt, the corresponding status bit will still be set in the Status Register so the user
can poll the status.
The Mask Register is used to control the activation of the INT pin. Placing a logic '1' in the Mask Register will
DRDY
)
ID1
23
15
7
2
2
-14
-1
2
14
16 (Current Channel AC Offset Register)
17 (Voltage Channel AC Offset Register)
15 (Status Register)
26 (Mask Register)
Binary: 000000000000000000000000 (Mask Register)
2
-15
-2
EOUT
IROR
ID0
22
14
6
2
2
-16
-3
2
2
-17
-4
VROR
EDIR
WDT
21
13
5
2
2
-18
-5
2
2
-19
-6
CRDY
EOR
VOD
20
12
4
2
2
-20
-7
.....
.....
EOOR
MATH
IOD
19
11
3
2
2
-17
-30
2
2
-18
-31
{x = state depends on device revision}
LSD
Res
Res
18
10
2
2
2
-19
-32
2
2
-20
-33
IOR
ID3
17
9
1
0
2
2
-21
-34
CS5460A
2
2
-22
-35
DS487F4
VOR
ID2
16
IC
8
0
LSB
LSB
2
2
-23
-36