EVAL-ADN2850-25EBZ Analog Devices Inc, EVAL-ADN2850-25EBZ Datasheet - Page 5

• Manufacturer Part Number: EVAL-ADN2850-25EBZ
• Description: BOARD EVALUATION FOR ADN2850-25
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADN2850-25EBZ

• Main Purpose: Digital Potentiometer
• Utilized Ic / Part: ADN2850-35
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

INTERFACE TIMING AND EEMEM RELIABILITY CHARACTERISTICS—25 kΩ, 250 kΩ VERSIONS
Guaranteed by design and not subject to production test. See the Timing Diagrams section for the location of measured values. All input
control voltages are specified with t
measured using both V
Table 2.
Parameter
Clock Cycle Time (t
C S
A
CLK Shutdown Time to
Input Clock Pulse Width
Data Setup Time
Data Hold Time
C S
A
C S
A
CLK to SDO Propagation Delay
CLK to SDO Data Hold Time
C S
A
C S
A
RDY Rise to
C S
A
Store EEMEM Time
Read EEMEM Time
C S
A
Preset Pulse Width (Asynchronous)
Preset Response Time to Wiper Setting
Power-On EEMEM Restore Time
FLASH/EE MEMORY RELIABILITY
1
2
3
4
5
6
7
8
Typicals represent average readings at 25°C and V
Propagation delay depends on the value of V
Valid for commands that do not activate the RDY pin.
RDY pin low only for Instruction 2, Instruction 3, Instruction 8, Instruction 9, Instruction 10, and the PR hardware pulse: CMD_8 ~ 20 μs; CMD_9, CMD_10 ~ 7 μs;
CMD_2, CMD_3 ~ 15 ms, PR hardware pulse ~ 30 μs.
Store EEMEM time depends on the temperature and EEMEM write cycles. Higher timing is expected at lower temperature and higher write cycles.
Not shown in Figure 2 and Figure 3.
Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C.
Retention lifetime equivalent at junction temperature (T
derates with junction temperature in the Flash/EE memory.
Endurance
Data Retention
E
A
E
A
E
A
E
A
E
E
A
E
A
Setup Time
to SDO-SPI Line Acquire
to SDO-SPI Line Release
High Pulse Width
H igh to
A
Rise to RDY Fall Time
Rise to Clock Rise/Fall Setup
C S
A
C S
A
7
E
A
High
E
A
Fall
8
4
CYC
4, 5
3
3
)
C S
A
DD
E
A
= 3 V and V
Rise
2
6
6
R
= t
6
DD
DD
F
, R
= 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are
= 5 V.
PULL-UP
DD
= 5 V.
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
6
7
8
9
10
11
12
13
14
15
16
16
17
PRW
PRESP
EEMEM
, t
, and C
J
5
) = 85°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV
L
.
Conditions
Clock level high or low
From positive CLK transition
From positive CLK transition
R
R
Applies to instructions 0x2, 0x3
Applies to instructions 0x8, 0x9, 0x10
P R
A
T
A
P
P
= 2.2 kΩ, C
= 2.2 kΩ, C
E
A
= 25°C
pulsed low to refresh wiper positions
Rev. C | Page 5 of 28
L
L
< 20 pF
< 20 pF
Min
20
10
1
10
5
5
0
10
4
0
10
50
100
Typ
0.15
15
7
30
30
1
100
1
Max
40
50
50
0.3
50
30
ADN2850
ms
Unit
ns
ns
t
ns
ns
ns
ns
ns
ns
ns
ns
t
ns
ms
μs
ns
ns
μs
μs
MCycles
kCycles
Years
CYC
CYC