ATA6613-EK Atmel, ATA6613-EK Datasheet - Page 238

• Manufacturer Part Number: ATA6613-EK
• Description: BOARD DEMO LIN-MCM FOR ATA6613
• Manufacturer: Atmel

Specifications of ATA6613-EK

• Main Purpose: Interface, LIN + MCU
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: ATA6613
• Primary Attributes: LIN-SBC (System-Basis-Chip) Transceiver, LIN 2.0, Voltage Regulator, Window Watchdog
• Secondary Attributes: 16 kB Flash, 4 Power Modes: Pre-Normal, Normal, Sleep, Silent, 48-QFN
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6.19.5.5
6.19.6
6.19.6.1
6.19.6.2
238
Atmel ATA6612/ATA6613
TWI Register Description
Control Unit
TWI Bit Rate Register – TWBR
TWI Control Register – TWCR
The Control unit monitors the TWI bus and generates responses corresponding to settings in
the TWI Control Register (TWCR). When an event requiring the attention of the application
occurs on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted. In the next clock cycle, the
TWI Status Register (TWSR) is updated with a status code identifying the event. The TWSR
only contains relevant status information when the TWI Interrupt Flag is asserted. At all other
times, the TWSR contains a special status code indicating that no relevant status information
is available. As long as the TWINT Flag is set, the SCL line is held low. This allows the appli-
cation software to complete its tasks before allowing the TWI transmission to continue.
The TWINT Flag is set in the following situations:
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate
a Master access by applying a START condition to the bus, to generate a Receiver acknowl-
edge, to generate a stop condition, and to control halting of the bus while the data to be written
to the bus are written to the TWDR. It also indicates a write collision if data is attempted written
to TWDR while the register is inaccessible.
• After the TWI has transmitted a START/REPEATED START condition.
• After the TWI has transmitted SLA+R/W.
• After the TWI has transmitted an address byte.
• After the TWI has lost arbitration.
• After the TWI has been addressed by own slave address or general call.
• After the TWI has received a data byte.
• After a STOP or REPEATED START has been received while still addressed as a Slave.
• When a bus error has occurred due to an illegal START or STOP condition.
• Bits 7..0 – TWI Bit Rate Register
• Bit 7 – TWINT: TWI Interrupt Flag
Initial Value
Initial Value
Read/Write
Read/Write
TWBR selects the division factor for the bit rate generator. The bit rate generator is a fre-
quency divider which generates the SCL clock frequency in the Master modes. See
Rate Generator Unit” on page 237
This bit is set by hardware when the TWI has finished its current job and expects applica-
tion software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump
to the TWI Interrupt Vector.
Bit
Bit
TWBR7
TWINT
R/W
R/W
7
0
7
0
TWBR6
TWEA
R/W
R/W
6
0
6
0
TWBR5
TWSTA
R/W
R/W
5
0
5
0
for calculating bit rates.
TWBR4
TWSTO
R/W
R/W
4
0
4
0
TWBR3
TWWC
R/W
3
0
R
3
0
TWBR2
TWEN
R/W
R/W
2
0
2
0
TWBR1
R/W
1
0
R
1
–
0
TWBR0
TWIE
R/W
R/W
0
0
0
0
9111H–AUTO–01/11
TWBR
TWCR
“Bit