Z8FMC160100KITG Zilog, Z8FMC160100KITG Datasheet - Page 141
Z8FMC160100KITG
Manufacturer Part Number
Z8FMC160100KITG
Description
KIT DEV FOR Z8 ENCORE Z8FMC16100
Manufacturer
Zilog
Series
Z8 Encore! MC™r
Datasheets
1.Z8FMC160100KIT.pdf
(7 pages)
2.Z8FMC160100KIT.pdf
(383 pages)
3.Z8FMC160100KITG.pdf
(2 pages)
4.Z8FMC160100KITG.pdf
(15 pages)
Specifications of Z8FMC160100KITG
Main Purpose
Power Management, Motor Control
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
Z8FMC16100
Primary Attributes
3-Ph DC Motors
Secondary Attributes
Graphical User Interface
For Use With
269-4664 - KIT ACC OPTO-ISO USB SMART CABLE269-4661 - KIT ACC ETHERNET SMART CABLE269-4539 - KIT ACCESSORY USB SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4660
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Table 68. LIN-UART Status 0 Register – Standard UART Mode (U0STAT0)
PS024613-0910
BITS
FIELD
RESET
R/W
ADDR
LIN-UART Status 0 Register
RDA
R
7
0
The LIN-UART Status 0 register identifies the current LIN-UART operating configuration
and status.
page 130 describes the Status0 register for LIN mode.
Receive Data Available (RDA)—
register has received data. Reading the LIN-UART Receive Data register clears this bit.
Parity Error (PE)—
Data register clears this bit.
Overrun Error (OE)—
occurs when new data is received and the Receive Data register has not been read. Reading
the Receive Data register clears this bit.
Framing Error (FE)—
reception) is detected. Reading the Receive Data register clears this bit.
Break Detect (BRKD)—
parity/multiprocessor bit, and STOP bit(s) are all zeros then this bit is set to 1. Reading the
Receive Data register clears this bit.
Transmitter Data Register Empty (TDRE)—
register is empty and ready for additional data. Writing to the Transmit Data register resets
this bit.
Transmitter Empty (TXE)—
character transmission is finished.
Clear To Send Signal (CTS)—
If LBEN = 1, the CTS input signal is replaced by the internal Receive Data Available
signal to provide flow control in loopback mode. CTS only affects transmission if the
CTSE bit = 1.
PE
Table 68
R
6
0
This bit indicates that a parity error has occurred. Reading the Receive
describes the Status 0 register for standard UART mode.
OE
This bit indicates that a framing error (no STOP bit following data
This bit indicates that an overrun error has occurred. An overrun
R
5
0
This bit indicates that a break has occurred. If the data bits,
This bit indicates that the transmit shift register is empty and
When this bit is read it returns the level of the CTS signal.
This bit indicates that the LIN-UART Receive Data
FE
R
4
0
F41H
BRKD
This bit indicates that the Transmit Data
R
3
0
Z8FMC16100 Series Flash MCU
TDRE
R
2
1
Product Specification
LIN-UART Status 0 Register
TXE
R
1
1
Table 69
CTS
X
R
0
on
129
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