ATWEBDVK-02RC Atmel, ATWEBDVK-02RC Datasheet - Page 39

• Manufacturer Part Number: ATWEBDVK-02RC
• Description: KIT DEV TCP/IP AT89C51RD2 REMOTE
• Manufacturer: Atmel
• Series: @Webr

Specifications of ATWEBDVK-02RC

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: AT89C51RD2
• Primary Attributes: *
• Secondary Attributes: *
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Figure 13-2. PCA Interrupt System
4235K–8051–05/08
PCA Timer/Counter
Module 0
Module 1
Module 2
Module 3
Module 4
CMOD.0
PCA Modules: each one of the five compare/capture modules has six possible functions. It can
perform:
In addition, Module 4 can be used as a Watchdog Timer.
Each module in the PCA has a special function register associated with it. These registers are:
CCAPM0 for Module 0, CCAPM1 for Module 1, etc. (See Table 13-3). The registers contain the
bits that control the mode that each module will operate in.
• 16-bit Capture, positive-edge triggered
• 16-bit Capture, negative-edge triggered
• 16-bit Capture, both positive and negative-edge triggered
• 16-bit Software Timer
• 16-bit High Speed Output
• 8-bit Pulse Width Modulator
• The ECCF bit (CCAPMn.0 where n = 0, 1, 2, 3, or 4 depending on the module) enables the
• PWM (CCAPMn.1) enables the pulse width modulation mode.
• The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to
• The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be
• The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a
• The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.
CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the
associated module.
toggle when there is a match between the PCA counter and the modules capture/compare
register.
set when there is a match between the PCA counter and the modules capture/compare
register.
capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit
enables the positive edge. If both bits are set both edges will be enabled and a capture will
occur for either transition.
ECF
CF
ECCFn CCAPMn.0
CR
CCF4 CCF3 CCF2 CCF1 CCF0
IEN0.6
EC
IEN0.7
EA
AT89C51RD2/ED2
Priority Decoder
CCON
0xD8
To Interrupt
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