ATAVRDISPLAYX Atmel, ATAVRDISPLAYX Datasheet - Page 4

• Manufacturer Part Number: ATAVRDISPLAYX
• Description: KIT EVAL XMEGA DISPLAY
• Manufacturer: Atmel

Specifications of ATAVRDISPLAYX

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: *
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Atmel
• Silicon Family Name: ATxmega
• Kit Contents: Board
• Features: Temperature Sensor, Mono Speaker Via Audio Amplifier
• Svhc: No SVHC (15-Dec-2010)
• Core Architecture: AVR
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.2 IO expansion headers
4
AVR1907
Table 4-1. XMEGA programming and debugging interface – JTAG and PDI.
The AT90USB1287 can be programmed through its bootloader. The bootloader is
evoked by shorting the (PORTF4) pin to GND before applying power to the board.
This can be done by shorting pin 1 and 2 on the “JTAG USB” pin header (J200) with a
jumper. Programming is performed through the “FLIP” plug-in in AVR Studio (can be
started as a stand-alone application also).
FLIP (FLexible In-system Programmer) is a free Atmel’s proprietary software that runs
Windows
of Flash devices through RS232, USB or CAN.
Alternatively, the AT90USB1287 can be also programmed by connecting a
programming tool, such as a JTAGICE mkII, to the “JTAG USB” pin header (J200).
Note that it is not recommended to program the AT90USB1287 using a
programming tool as this will erase the bootloader.
The XMEGA’s analog PORTA is available on the “XMEGA PORT A” pin header
(J101). This allows the user to connect external signals to the ADC, DAC and Analog
Comparators on PORTA.
The XMEGA’s digital PORTD is available on the “XMEGA PORT D” pin header
(J102). This port features general purpose IO and various communication modules
(USART, SPI and TWI).
Note that the communication modules on PORTD can be interconnected to test out
various functions and features: The USART can loop back communication with a
jumper, or communicate between the two UARTs on the PORT. The native SPI and
the USART in SPI master mode can be connected, and the TWI module can be
enabled in both master and slave mode at the same time to get loop back behavior
(pull-up resistors required).
J100 pin
J100-1
J100-2
J100-3
J100-4
J100-5
J100-6
J100-7
J100-8
J100-9
J100-10
Notes:
®
1. Standard pin-out for JTAGICE mkII and other Atmel programming tools.
2. Requires adapter to connect a JTAGICE mkII (refer to AVR Studio help).
3. It is only required to connect on VCC/GND pin.
9x/Me/NT/2000/XP and Linux x86. FLIP supports in-system programming
JTAG
TCK
GND
TDO
VCC
TMS
nSRST
VCC
-
TDI
GND
(1)
PDI
-
GND
-
VCC
-
CLK
VCC
DATA
-
GND
(2)
(3)
(3)
(3)
(3)
8203D-AVR-04/10