Z86E4001ZDV Zilog, Z86E4001ZDV Datasheet - Page 57

• Manufacturer Part Number: Z86E4001ZDV
• Description: 44 PIN PLCC ADAPTER
• Manufacturer: Zilog

Specifications of Z86E4001ZDV

• Module/board Type: ZIF Socket
• Processor Series: Z86E4xx
• Core: Z8
• Data Bus Width: 8 bit
• Program Memory Type: ROM
• Program Memory Size: 4 KB
• Data Ram Size: 236 KB
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 3.5 V to 5.5 V
• Mounting Style: SMD/SMT
• Package / Case: LQFP-44
• Development Tools By Supplier: Z86CCP01ZEM, Z86C4001ZDV, Z86E4001ZDV, Z86E4001ZDF, Z86CCP00ZAC
• For Use With/related Products: Zilog Emulators/Programmers
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-2008

Z8 CONTROL REGISTER DIAGRAMS (Continued)
Z86E30/E31/E40
Z8 4K OTP Microcontroller
58
R246 P2M
R247 P3M
* Default After Reset
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Default After Reset = 00H
† Z86E30/E31 Must Be 00
Figure 51. Port 2 Mode Register
Figure 52. Port 3 Mode Register
F6H: Write Only
F7H: Write Only
00
01
10
11
0 P30 = Input
0 Port 2 Open-Drain
1 Port 2 Push-pull Active
0 P31, P32 Digital Mode
1 P31, P32 Analog Mode
0 P32 = Input
1 P32 = DAV0/RDY0
Reserved (Must be 0)
0 P31 = Input (TIN)
1 P31 = DAV2/RDY2
P20 - P27 I/O Definition
P37 = Output
0 Defines Bit as Output
1 Defines Bit as Input*
P35 = Output
P35 = RDY0/DAV0
P36 = Output (TOUT)
P36 = RDY2/DAV2
P33 = DAV1/RDY1
P33 = Input
P34 = Output
P33 = Input
P34 = DM
P34 = RDY1/DAV1
P R E L I M I N A R Y
†
R248 P01M
D7 D6 D5 D4 D3 D2 D1 D0
R249 IPR
D7 D6 D5 D4
Reset Condition = 0100 1101B
For ROMless Condition = 1011 0110B
† Z86E30/E31 Must be 00
Figure 53. Port 0 and 1 Mode Register
Figure 54. Interrupt Priority Register
D3 D2 D1 D0
Z86E30/E31 Only
F8H: Write Only
F9H: Write Only
P17 – P10 Mode
P03 – P00 Mode
Stack Selection
External Memory Timing
P07 – P04 Mode
Interrupt Group Priority
IRQ1, IRQ4 Priority (Group C)
IRQ0, IRQ2 Priority (Group B)
IRQ3, IRQ5 Priority (Group A)
Reserved (Must be 0)
00
01
1X
00
01
1X A11–A8
00
01
10
11
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
0
1
0
1
Byte Output†
Byte Input
AD7–AD0
High-Impedance AD7–AD0,
AS, DS, R/W, A11–A8,
A15–A12, If Selected
Output
Input
External
Internal
Normal
Extended
Output
Input
A15 - A12
DS97Z8X0502
Zilog