CY3724 Cypress Semiconductor Corp, CY3724 Datasheet - Page 4

• Manufacturer Part Number: CY3724
• Description: SOCKET ADAPTER FOR CY25701
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY3724

• Accessory Type: Socket Adapter
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: CY3672, CY25701FJXC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

AC Electrical Characteristics
Application Circuit
Switching Waveforms
Document Number: 001-07313 Rev. *E
Notes
DC
t
t
T
T
T
T
R
F
3. Jitter is configuration dependent. Actual jitter depends upon output frequencies, spread percentage, temperature, and output load. For more information, see the
Parameter
CCJ1
OE1
OE2
LOCK
application note, “Jitter in PLL Based Systems: Causes, Effects, and Solutions” available at
Field Application Engineer.
[3]
Output Duty Cycle
Output Rise Time
Output Fall Time
Cycle-to-Cycle Jitter SSCLK
(Pin 3)
Output Disable Time (pin1 = OE) Time from falling edge on OE to stopped
Output Enable Time (pin1 = OE)
PLL Lock Time
Description
Duty Cycle Timing (DC = t1A/t1B)
SSCLK
[2]
Figure 2. Application Circuit Diagram
Figure 3. Duty Cycle Waveform
20%–80% of V
20%–80% of V
SSCLK, Measured at V
SSCLK 133 MHz, Measured at V
25 MHz SSCLK <133 MHz, Measured at
V
SSCLK < 25 MHz, Measured at V
outputs (Asynchronous)
Time from rising edge on OE to outputs at a
valid frequency (Asynchronous)
Time for SSCLK to reach valid frequency
Power
DD
/2
VDD
VDD
OE
1
4
CY25701
0.1 µF
t
DD,
DD,
1A
Condition
C
C
SSCLK
L
L
VSS
t
1B
= 15 pF
= 15 pF
3
2
DD
http://www.cypress.com/clock/appnotes.html
/2
DD
DD
/2
/2
Min
45
–
–
–
–
–
–
–
–
Typ
215
150
150
50
85
–
–
–
–
or contact your local Cypress
1/SSCK
1% of
Max
200
400
350
350
2.7
2.7
55
10
CY25701
Page 4 of 9
Unit
ms
ns
ns
ns
ns
ps
ps
%
s
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