LTM4601HVIV#PBF Linear Technology, LTM4601HVIV#PBF Datasheet - Page 19

IC DC/DC UMODULE 12A 118-LGA

LTM4601HVIV#PBF

Manufacturer Part Number
LTM4601HVIV#PBF
Description
IC DC/DC UMODULE 12A 118-LGA
Manufacturer
Linear Technology
Series
µModuler
Type
Point of Load (POL) Non-Isolatedr
Datasheet

Specifications of LTM4601HVIV#PBF

Design Resources
LTM4601HV Spice Model
Output
0.6 ~ 5 V
Number Of Outputs
1
Power (watts)
60W
Mounting Type
Surface Mount
Voltage - Input
4.5 ~ 28 V
Package / Case
118-LGA
1st Output
0.6 ~ 5 VDC @ 12A
Size / Dimension
0.59" L x 0.59" W x 0.11" H (15mm x 15mm x 2.8mm)
Power (watts) - Rated
60W
Operating Temperature
-40°C ~ 85°C
Efficiency
95%
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
3rd Output
-
2nd Output
-
Other names
LTM4601HEIV#PBF
LTM4601HEIV#PBF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LTM4601HVIV#PBF
Manufacturer:
LT
Quantity:
900
Company:
Part Number:
LTM4601HVIV#PBF/HVEV
Manufacturer:
LT
Quantity:
23
APPLICATIONS INFORMATION
to 25°C inside the μModule with a thermal resistance θ
from junction to case between 6°C/W to 9°C/W. This will
maintain the maximum junction temperature inside the
μModule below 125°C.
Safety Considerations
The LTM4601HV modules do not provide isolation from
V
slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure.
Layout Checklist/Example
The high integration of LTM4601HV makes the PCB board
layout very simple and easy. However, to optimize its electri-
cal and thermal performance, some layout considerations
are still necessary.
• Use large PCB copper areas for high current path, in-
IN
cluding V
PCB conduction loss and thermal stress.
to V
OUT
IN
. There is no internal fuse. If required, a
, PGND and V
OUT
. It helps to minimize the
V
GND
V
OUT
IN
C
OUT
C
IN
Figure 17. Recommended Layout
C
OUT
C
IN
JC
• Place high frequency ceramic input and output capaci-
• Place a dedicated power ground layer underneath the
• To minimize the via conduction loss and reduce module
• Do not put vias directly on pads unless they are
• Use a separated SGND ground copper area for com-
Figure 17 gives a good example of the recommended
layout.
tors next to the V
high frequency noise.
unit. Refer frequency synchronization source to power
ground.
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
capped.
ponents connected to signal pins. Connect the SGND
to PGND underneath the unit.
4601HV F17
IN
SIGNAL
GND
, PGND and V
LTM4601HV
OUT
pins to minimize
19
4601hvfa

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