PS12018-A Powerex Inc, PS12018-A Datasheet - Page 5

• Manufacturer Part Number: PS12018-A
• Description: IC CONV AC-DC 3-PHASE 1200V 25A
• Manufacturer: Powerex Inc

Specifications of PS12018-A

• Voltage - Output: 1200V
• Number Of Outputs: 1
• Power (watts): 30000W
• Applications: Commercial
• Power Supply Type: Switching (Closed Frame)
• Voltage - Input: 900VAC
• Mounting Type: Through Hole
• 1st Output: 1200 VDC @ 25A
• Size / Dimension: 2.99" L x 4.53" W x 0.33" H (76mm x 115mm x 8.5mm)
• Power (watts) - Rated: 30000W
• Operating Temperature: -20°C ~ 100°C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING
Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART
Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simulta-
Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION
Note : Shor t circuit protection operation. The protection operates with “F
neously in “LOW” level.
By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and “F
interlock” operation the circuit is latched. The “F
whichever comes in later.
gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the “Brake”).
LINEARITY
V
Input signal V
Input signal V
Gate signal V
(ASIPM internal)
Gate signal V
(ASIPM internal)
C
–400
5
–
4
3
2
1
0
min
Real load current peak value.(%)(I
–300
Input signal V
upper arm
Short circuit sensing signal V
Gate signal Vo of each phase
upper arm(ASIPM internal)
max
–200
CIN(p)
CIN(n)
o(p)
o(n)
Analogue output signal
–100
of each phase upper arm
of each phase upper arm
V
data hold range
C
of each phase upper arm
of each phase lower arm
–
(200%)
CIN
Error output F
0
of each phase
Error output F
V
C0
100
V
V
T
200
C
DH
DL
O1
=
c
=5V
S
=15V
–
V
=I
20
C
o
+(200%)
300
~
O1
100˚C
0V
0V
0V
0V
2)
400
V
0V
0V
0V
0V
0V
C
O
” is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input,
+
Note ; Ringing happens around the point where the signal output
Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING
O
” flag and reset on a pulse-by-pulse scheme. The protection by
voltage changes state from “analogue” to “data hold” due
to test circuit arrangement and instrumentational trouble.
Therefore, the rate of change is measured at a 5 s delayed point.
“DATA HOLD” DEFINITION
0V
V
C
S
r
C
CH
delay time
=
V
CH
V
(5 s)
CH
(505 s)-V
V
500 s
CH
O
” signal is outputted. After an “input
(5 s)
CH
(5 s)
V
INSULATED TYPE
CH
PS12018-A
FLAT-BASE TYPE
(505 s)
Jan. 2000