M0216SD-162SDAR8 Newhaven Display, M0216SD-162SDAR8 Datasheet - Page 13

• Manufacturer Part Number: M0216SD-162SDAR8
• Description: MODULE VF CHAR 2X16 5.34MM
• Manufacturer: Newhaven Display

Specifications of M0216SD-162SDAR8

• Outline L X W X H: 84.00mm x 44.00mm x 16.60mm
• Display Format: 16 x 2
• Display Type: Character
• Format: 5 x 8 Dots
• Voltage - Supply: 5V
• Character Size: 5.34mm H x 2.10mm W
• Operating Temperature: -40°C ~ 85°C
• Product: Character Display Modules
• Character Count X Line: 16 x 2
• Module Size (w X H X T): 84 mm x 44 mm x 16.6 mm
• Voltage Rating: 5 V
• Operating Temperature Range: - 40 C to + 85 C
• Dot Format: 5 x 7
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Interface: -
• Viewing Area: -
• Number Of Dots: -
• Lead Free Status / Rohs Status: Details

STANDARD
NAME
4.1.2 INTEL I80-TYPE MODE
This mode uses the Read (RD/) and Write (WR/) control signals to transfer information.
Instructions/data are written to the modules on the rising edge of WR/ and are read from the modules
after the falling edge of RD/.
4.2 SYNCHRONOUS SERIAL INTERFACE MODE
In the synchronous serial interface mode, instructions and data are sent between the host and the
modules using 8-bit bytes. Two bytes are required per read/write cycle and are transmitted MSB first.
The start byte contains 5 high bits, the Read/Write (R/W) control bit, the Register Select (RS) control
bit, and a low bit. The following byte contains the instruction/data bits. The R/W bit determines
whether the cycle is a read (high) or a write (low) cycle. The RS bit is used to identify the second byte
as an instruction (low) or data (high).
This mode uses the Strobe (STB) control signal, Serial Clock (SCK) input, and Serial I/O (SI/SO) line
to transfer information. In a write cycle, bits are clocked into the modules on the rising edge of SCK.
In a read cycle, bits in the start byte are clocked into the modules on the rising edge of SCK. After the
minimum wait time, each bit in the instruction/data byte can be read from the modules after each falling
edge of SCK. Each read/write cycle begins on the falling edge of STB and ends on the rising edge. To
be a valid read/write cycle, the STB must go high at the end of the cycle.
W R /
D B 7
D B 6
D B 0
R D /
R S
W r i t e i n s t r u c t i o n
Figure 10. Typical 8-Bit Parallel Interface Sequence Using I80-Type Mode
SPECIFICATION FOR APPROVAL
IB7
IB6
IB0
W r i t e i n s t r u c t i o n
IB7
IB6
IB0
R e a d i n s t r u c t i o n
DOCUMENT NO.
BF= ' 0 '
M0216SD-162SDAR8
IB6
IB0
W r i t e d a t a
D B 7
D B 6
D B 0
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