HYS64T64000HU-3S-B Qimonda, HYS64T64000HU-3S-B Datasheet - Page 28
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HYS64T64000HU-3S-B
Manufacturer Part Number
HYS64T64000HU-3S-B
Description
MODULE DDR2 512MB 240-DIMM
Manufacturer
Qimonda
Datasheet
1.HYS64T64000HU-3S-B.pdf
(87 pages)
Specifications of HYS64T64000HU-3S-B
Memory Type
DDR2 SDRAM
Memory Size
512MB
Speed
333MHz
Package / Case
240-DIMM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
675-1023
Rev. 1.3, 2006-12
03292006-6GMD-RSFT
Parameter
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge
time
Minimum time clocks remain ON after CKE
asynchronously drops LOW
DQ and DM input hold time (differential data
strobe)
DQ and DM input hold time (single ended data
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ
signals)
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data
strobe)
DQ and DM input setup time (single ended data
strobe)
DQS falling edge hold time from CK (write
cycle)
DQS falling edge to CK setup time (write cycle)
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
DRAM Component Timing Parameter by Speed Grade - DDR2–533
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AC
CCD
CH
CKE
CL
DAL
DELAY
DH
DH1
DIPW
DQSCK
DQSL,H
DQSQ
DQSS
DS
DS1
DSH
DSS
HP
HZ
IH
IPW
IS
LZ(DQ)
LZ(DQS)
MRD
OIT
QH
QHS
REFI
(base)
(base)
(base)
(base)
(base)
(base)
28
HYS[64/72]T[32/64/128]xx0HU-[25F/2.5/3/3S/3.7/5]-B
DDR2–533
–500
2
0.45
3
0.45
WR +
t
225
–25
0.35
–450
0.35
—
– 0.25
100
–25
0.2
0.2
MIN. (
—
375
0.6
250
2 ×
t
2
0
t
—
—
Min.
IS
AC.MIN
HP
+
–
t
t
AC.MIN
t
CK
QHS
t
t
CL,
RP
+
t
t
CH
IH
)
Max.
+500
—
0.55
—
0.55
—
—
—
—
—
+450
—
300
+ 0.25
—
—
—
—
t
—
—
—
t
t
—
12
—
400
7.8
AC.MAX
AC.MAX
AC.MAX
Unbuffered DDR2 SDRAM Module
Unit
ps
t
t
t
t
t
ns
ps
ps
t
ps
t
ps
t
ps
ps
t
t
ps
ps
t
ps
ps
ps
t
ns
—
ps
µs
Internet Data Sheet
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
CK
TABLE 18
Note
1)2)3)4)5)6)7)
8)18)
9)
10)
11)
11)
11)
11)
12)
13)
11)
11)
14)
14)
14)15)