MT8JTF12864AY-1G4D1 Micron Technology Inc, MT8JTF12864AY-1G4D1 Datasheet - Page 6

• Manufacturer Part Number: MT8JTF12864AY-1G4D1
• Description: MODULE DDR3 SDRAM 1GB 240-UDIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8JTF12864AY-1G4D1

• Memory Type: DDR3 SDRAM
• Memory Size: 1GB
• Speed: 1333MT/s
• Package / Case: 240-UDIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

General Description
Fly-By Topology
Serial Presence-Detect EEPROM Operation
PDF: 09005aef82b21119/Source: 09005aef82b2112c
JTF8c128_256x64AY.fm - Rev. B 6/08 EN
The MT8JTF12864A and MT8JTF25664A DDR3 SDRAM modules are high-speed, CMOS
dynamic random access 1GB and 2GB memory modules organized in a x64 configura-
tion. These DDR3 SDRAM modules use internally configured, 8-bank 1Gb and 2Gb
DDR3 SDRAM devices.
DDR3 SDRAM modules use double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially an 8n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR3 SDRAM module effectively consists of a single
8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the
data strobes.
DDR3 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Control, command, and address signals are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
These DDR3 modules use faster clock speeds than earlier DDR technologies, making
signal quality more important than ever. For improved signal quality, the clock, control,
command, and address busses have been routed in a fly-by topology, where each clock,
control, command, and address pin on each DRAM is connected to a single trace and
terminated (rather than a tree structure, where the termination is off the module near
the connector). Inherent to fly-by topology, the timing skew between the clock and DQS
signals can be easily accounted for by utilizing the write-leveling feature of DDR3.
DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with JEDEC
specification JC-45 “Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM
Modules.” These bytes identify module-specific timing parameters, configuration infor-
mation, and physical attributes. User-specific information can be written into the
remaining 128 bytes of storage. System READ/WRITE operations between the master
(system logic) and the slave EEPROM device occur via a standard I
DIMM’s SCL (clock) and SDA (data) signals, together with SA[2:0], which provide eight
unique DIMM/EEPROM addresses. Write protect (WP) is connected to V
disabling hardware write protect.
1GB, 2GB (x64, SR) 240-Pin DDR3 SDRAM UDIMM
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2007 Micron Technology, Inc. All rights reserved
2
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