MT36VDDF25672Y-335F3 Micron Technology Inc, MT36VDDF25672Y-335F3 Datasheet - Page 14

• Manufacturer Part Number: MT36VDDF25672Y-335F3
• Description: MODULE DDR 2GB 184-RDIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36VDDF25672Y-335F3

• Memory Type: DDR SDRAM
• Memory Size: 2GB
• Speed: 166MHz
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 256Mx72
• Total Density: 2GByte
• Chip Density: 512Mb
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 3.24A
• Number Of Elements: 36
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1343

Commands
Table 11:, DM Operation Truth Table, provide a general
reference of available commands. For a more detailed
Table 10: Commands Truth Table
CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved
NOTE:
Table 11: DM Operation Truth Table
Used to mask write data; provided coincident with the corresponding data
pdf: 09005aef80772fd2, source: 09005aef8075ebf6
DDF36C128_256x72G.fm - Rev. D 9/04 EN
NAME (FUNCTION)
NAME (FUNCTION)
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
WRITE Enable
WRITE Inhibit
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide device bank address and A0–A12 provide row address.
3. BA0–BA1 provide device bank address; A0–A9, A11 (1GB) or A0–A9, A11, A12 (2GB) provide column address; A10 HIGH
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ
5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0–
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0
Table Table 10:, Commands Truth Table, and Table
enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
bursts with auto precharge enabled and for WRITE bursts.
BA1 are “Don’t Care.”
= 1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A12 provide the op-code
to be written to the selected mode register.
14
CS#
description of commands and operations, refer to the
256Mb or 512Mb DDR SDRAM component data sheet.
H
L
L
L
L
L
L
L
L
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RAS#
X
H
H
H
H
L
L
L
L
1GB, 2GB (x72, ECC, DR)
CAS#
H
H
H
H
X
L
L
L
L
184-PIN DDR RDIMM
WE#
X
H
H
H
H
L
L
L
L
©2004 Micron Technology, Inc. All rights reserved.
Bank/Row
Bank/Col
Bank/Col
Op-Code
ADDR
Code
DM
X
X
X
X
H
L
NOTES
Valid
DQS
6, 7
X
1
1
2
3
3
4
5
8