MT18HVF12872PY-667D1 Micron Technology Inc, MT18HVF12872PY-667D1 Datasheet - Page 9

• Manufacturer Part Number: MT18HVF12872PY-667D1
• Description: MODULE DDR2 512MB 240-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18HVF12872PY-667D1

• Memory Type: DDR2 SDRAM
• Memory Size: 1GB
• Speed: 667MT/s
• Package / Case: 240-DIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 512Mb
• Access Time (max): 45ps
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 3.24A
• Number Of Elements: 18
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
Table 8:
PDF: 09005aef82255aba/Source: 09005aef82255a83
HVF18C64_128_256x72G.fm - Rev. B 5/06 EN
Parameter/Condition
Operating one bank active-precharge current;
(I
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current; I
CL = CL (I
t
bus inputs are switching; Data pattern is same as I
Precharge power-down current; All device banks idle;
is LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge quiet standby current; All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data
bus inputs are floating
Precharge standby current; All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
Active power-down current; All device banks open;
t
inputs are stable; Data bus inputs are floating
Active standby current; All device banks open;
MAX (I
Other control and address bus inputs are switching; Data bus inputs are
switching
Operating burst write current; All device banks open, Continuous burst
writes; BL = 4, CL = CL (I
t
inputs are switching; Data bus inputs are switching
Operating burst read current; All device banks open, Continuous burst
reads, I
MAX (I
Address bus inputs are switching; Data bus inputs are switching
Burst refresh current;
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current; All device banks interleaving
reads, I
(I
HIGH between valid commands; Address bus inputs are stable during
DESELECTs; Data bus inputs are switching
DD
RCD =
CK =
RP =
DD
DD
),
),
Specifications
t
t
t
t
RP (I
RAS =
RC =
CK (I
DD
DD
OUT
OUT
t
RCD (I
DD
),
),
DD
= 0mA; BL = 4, CL = CL (I
DD
t
= 0mA; BL = 4, CL = CL (I
t
t
), AL = 0;
RP =
RP =
RC (I
t
); CKE is HIGH, S# is HIGH between valid commands; Address bus
RAS MIN (I
DDR2 I
Values shown for MT47H128M4 DDR2 SDRAM only and are computed from values specified in the 512Mb
(128 Meg x 4) component data sheet
); CKE is LOW; Other control and address bus
DD
); CKE is HIGH, S# is HIGH between valid commands; Address
DD
t
t
RP (I
RP (I
),
t
t
Notes: 1. a = Value calculated as one module rank in this operating condition, and all other module
CK =
RRD =
DD
DD
DD
DD
DD
t
); CKE is HIGH, S# is HIGH between valid commands;
); CKE is HIGH, S# is HIGH between valid commands;
CK =
Specifications and Conditions – 1GB
), AL = 0;
); CKE is HIGH, S# is HIGH between valid
t
CK (I
t
2. b = Value calculated reflects all module ranks in this operating condition.
RRD (I
t
CK (I
DD
DD
),
DD
DD
DD
t
ranks in I
CK =
t
), AL =
RC =
); REFRESH command at every
),
), AL = 0;
t
RCD =
t
CK (I
t
RC (I
t
RCD (I
DD
DD
t
t
2
RCD (I
DD
CK =
P
),
t
DD
(CKE LOW) mode.
DD
),
CK =
t
t
RAS =
t
CK =
t
4W
) -1 ×
RAS =
CK =
t
DD
CK (I
t
CK (I
); CKE is HIGH, S# is
t
t
OUT
CK =
CK (I
t
t
t
DD
t
CK (I
CK (I
RAS MAX (I
t
CK =
RAS MIN (I
1GB (x72, ECC, SR) 240-Pin DDR2 VLP RDIMM
9
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
DD
),
= 0mA; BL = 4,
DD
t
t
),
DD
DD
RAS =
CK (I
t
t
),
CK (I
RAS =
); CKE is
);
t
t
t
RC =
RFC (I
DD
CK =
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
t
DD
DD
RAS
); CKE
t
);
RAS
t
),
),
t
RC
DD
CK
)
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
DD
DD
DD
I
I
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
2P
3P
4R
0
1
5
6
7
b
b
a
a
a
b
b
a
b
b
b
a
-667
1,620
1,890
1,170
3,060
3,240
3,240
4,320
126
810
900
630
216
126
©2003 Micron Technology, Inc. All rights reserved.
I
DD
1,440
1,710
2,520
2,610
3,060
4,050
-53E
126
720
810
540
216
990
126
Specifications
1,440
1,620
2,070
2,070
2,970
3,960
-40E
126
630
720
450
216
810
126
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA