MT18HTF12872PY-80ED2 Micron Technology Inc, MT18HTF12872PY-80ED2 Datasheet - Page 14

• Manufacturer Part Number: MT18HTF12872PY-80ED2
• Description: MODULE DDR2 1GB 240-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18HTF12872PY-80ED2

• Memory Type: DDR2 SDRAM
• Memory Size: 1GB
• Speed: 800MT/s
• Package / Case: 240-DIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 512Mb
• Access Time (max): 40ps
• Maximum Clock Rate: 800MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 3.69A
• Number Of Elements: 18
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Presence-Detect
Table 17:
Table 18:
PDF: 09005aef80e5e752/Source: 09005aef80e5e626
HTF18C64_128_256x72.fm - Rev. E 3/07 EN
Parameter/Condition
Parameter/Condition
Supply voltage
Input high voltage: Logic 1; All inputs
Input low voltage: Logic 0; All inputs
Output low voltage: I
Input leakage current: V
Output leakage current: V
Standby current
Power supply current, READ: SCL clock frequency = 100 kHz
Power supply current, WRITE: SCL clock frequency = 100 kHz
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
Notes:
OUT
IN
= 3mA
OUT
= GND to V
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
2. This parameter is sampled.
3. For a restart condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
= GND to V
the falling or rising edge of SDA.
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tance, and the EEPROM does not respond to its slave address.
512MB, 1GB, 2GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
DD
SS
SS
DD
; V
; V
DDSPD
DDSPD
= +1.7V to +3.6V
= +1.7V to +3.6V
14
t
Symbol
Symbol
t
t
t
t
HD:DAT
V
HD:STA
SU:DAT
SU:STA
SU:STO
t
t
t
t
t
HIGH
DDSPD
LOW
f
WRC
I
t
t
WRC) is the time from a valid stop condition of a write
V
I
BUF
V
V
I
CC
SCL
I
AA
DH
CC
I
t
t
LO
SB
t
OL
LI
R
IH
F
I
IL
Micron Technology, Inc., reserves the right to change products or specifications without notice.
W
R
V
Min
DDSPD
200
100
0.2
1.3
0.6
0.6
1.3
0.6
0.6
–
0
–
–
–
–
Min
–0.6
0.10
0.05
1.7
1.6
0.4
2
–
× 0.7
Max
300
400
Serial Presence-Detect
0.9
0.3
50
10
–
–
–
–
–
–
–
–
–
©2003 Micron Technology, Inc. All rights reserved.
V
V
DDSPD
DDSPD
Max
3.6
0.4
Units
3
3
4
1
3
kHz
ms
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
+ 0.5
× 0.3
Notes
Units
mA
mA
µA
µA
µA
1
2
2
3
4
V
V
V
V