MT36HTS51272FY-667A3E3 Micron Technology Inc, MT36HTS51272FY-667A3E3 Datasheet - Page 26

• Manufacturer Part Number: MT36HTS51272FY-667A3E3
• Description: MODULE DDR2 4GB 240FBDIMM
• Manufacturer: Micron Technology Inc

Specifications of MT36HTS51272FY-667A3E3

• Memory Type: DDR2 SDRAM
• Memory Size: 4GB
• Speed: 667MT/s
• Package / Case: 240-FBDIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PDF: 09005aef822148b0/source: 09005aef82214898
HTS36C512x72F_2.fm - Rev. A 4/06 EN
V
RX
10. Allows for 15mV DC offset between transmit and receive devices.
11. The received differential signal must satisfy both this ratio as well as the absolute maximum
12. One of the components that contribute to the deterioration of the return loss is the ESD
13. The termination small signal resistance; tolerance across voltages from 100mV to 400mV
14. This number represents the lane-to-lane skew between TX and RX pins and does not
15. Measured from the reference clock edge to the center of the input eye. This specification
16. This bandwidth number assumes the specified minimum data transition density. Maximum
17. The specified time includes the time required to forward the EI entry condition.
18. BER per differential lane. Refer to Section 4 of the JEDEC specification for a complete defi-
-
5. See Figure 3-8 and Figure 3-9 of the JEDEC specification. The single-pulse mask provides suf-
6. See Figure 3-10 of the JEDEC specification. The relative amplitude ratio limit between adja-
7. This number does not include the effects of SSC or reference clock jitter.
8. This number includes setup and hold of the RX sampling flop.
9. Defined as the dual-dirac deterministic timing error.
CM
R
RX
-
ficient symbol energy for reliable RX reception. Each symbol must comply with both the sin-
gle-pulse mask and the cumulative eyemask.
cent symbols prevents excessive intersymbol interference in the RX. Each symbol must com-
ply with the peak amplitude ratio with regard to both the preceding and subsequent
symbols.
AC peak-to-peak common mode specification. For example, if VRX-DIFFp-p is 200mV, the
maximum AC peak-to peak common mode is the lesser of (200mV × 0.45 = 90mV) and VRX-
CM-AC-p-p.
structure which must be carefully designed.
shall not exceed ±5W with regard to the average of the values measured at 100mV and at
400mV for that pin.
include the transmitter output skew from the component driving the signal to the receiver.
This is one component of the end-to-end channel skew in the AMB specification.
must be met across specified voltage and temperature ranges for a single component. Drift
rate of change is significantly below the tracking capability of the receiver.
jitter at 0.2 MHz is 0.05 UI, see Section 4 of the JEDEC specification for full jitter tolerance
mask.
nition of bit error ratio.
AC
-
MATCH
= ((MAX |V
(V
-
RX
DC
-
V
CM
= 2 x ((|R
RX
-
= DC
RX
DIFF
-D+
p-p
Differential Transmitter and Receiver Specifications
(AVG)
+ V
RX
= 2 x |V
-D+
RX
240-Pin 4GB DDR2 SDRAM FBDIMM (DR, FB, x72)
of |V
-D-
- R
|)/2)((MIN |V
26
RX
RX
RX
-D+
-D-
-D+
|)/(R
- V
+ V
RX
RX
Micron Technology, Inc., reserves the right to change products or specifications without notice.
RX
-D-
-D-
-D+
RX
|
|/2)
-D+
+ R
+ V
RX
-D-
RX
-D-
|))
|)/2)
©2006 Micron Technology, Inc. All rights reserved.
Preliminary
(EQ 5)
(EQ 6)
(EQ 7)
(EQ 8)