MT18VDVF12872Y-40BF1 Micron Technology Inc, MT18VDVF12872Y-40BF1 Datasheet - Page 8

• Manufacturer Part Number: MT18VDVF12872Y-40BF1
• Description: MODULE DDR 1GB 184-DIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT18VDVF12872Y-40BF1

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 512Mb
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 3.51A
• Number Of Elements: 18
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
Table 8:
PDF: 09005aef81c7380b/Source: 09005aef81c7380e
DVF18C_128x72.fm - Rev. C 11/07 EN
Parameter/Condition
Operating one bank active-precharge current:
DQ and DQS inputs changing once per clock cycle; Address and control inputs changing
once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
Precharge power-down standby current: All device banks idle; Power-down mode;
t
Idle standby current: CS# = HIGH; All device banks idle;
Address and other control inputs changing once per clock cycle; V
DQS
Active power-down standby current: One device bank active; Power-down mode;
t
Active standby current: CS# = HIGH; CKE = HIGH; One device bank active;
t
Address and other control inputs changing once per clock cycle
Operating burst READ current: BL = 2; Continuous burst READs; One device bank
active; Address and control inputs changing once per clock cycle;
I
Operating burst WRITE current: BL = 2; Continuous burst WRITEs; One device bank
active; Address and control inputs changing once per clock cycle;
and DQS inputs changing twice per clock cycle
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave READ current: Four device bank interleaving READs
(BL = 4) with auto precharge;
inputs change only during active READ or WRITE commands
DD
OUT
CK =
CK =
CK =
RC =
Specifications
= 0mA
t
t
t
t
RAS (MAX);
CK (MIN); I
CK (MIN); CKE = LOW
CK (MIN); CKE = LOW
I
Values are shown for the MT46V128M4 DDR SDRAM only and are computed from values specified in the
512Mb (128 Meg x 4) component data sheet
DD
OUT
Specifications and Conditions – 1GB
t
CK =
= 0mA; Address and control inputs changing once per clock cycle
t
CK (MIN); DQ and DQS inputs changing twice per clock cycle;
t
RC =
t
RC (MIN);
t
CK =
t
RC =
t
CK (MIN); Address and control
t
t
RC (MIN);
CK =
8
1GB (x72, ECC, SR): 184-Pin DDR VLP RDIMM
t
t
REFC =
REFC = 7.8125µs
t
CK (MIN); CKE = HIGH;
t
IN
RC =
t
t
CK =
CK =
= V
t
CK =
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
REF
t
RC (MIN);
RFC (MIN)
t
t
CK (MIN);
CK (MIN); DQ
for DQ and
t
CK (MIN);
Symbol
Electrical Specifications
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
3N
5A
4R
2P
2F
3P
0
1
5
6
7
©2005 Micron Technology, Inc. All rights reserved
2,790
3,330
1,080
3,420
3,510
6,210
8,100
-40B
990
810
198
90
90
2,340
2,880
2,970
3,150
5,220
7,290
-335
810
630
900
180
90
90
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA