MT4HTF6464AY-40EA1 Micron Technology Inc, MT4HTF6464AY-40EA1 Datasheet - Page 12

• Manufacturer Part Number: MT4HTF6464AY-40EA1
• Description: MODULE SDRAM DDR2 512MB 240DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4HTF6464AY-40EA1

• Memory Type: DDR2 SDRAM
• Memory Size: 512MB
• Speed: 400MT/s
• Package / Case: 240-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 11: DDR2 I
Values shown for MT47H32M16 DDR2 SDRAM only and are computed from values specified in the 512Mb (32 Meg x 16)
component data sheet
PDF: 09005aef80ed6fda
htf4c16_32_64x64ay – Rev. H 3/10 EN
Parameter
Operating one bank active-precharge current:
t
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
4, CL = CL (I
(I
Address bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
CKE is LOW; Other control and address bus inputs are stable; Data bus in-
puts are floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable;
Data bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Da-
ta bus inputs are switching
Active power-down current: All device banks open;
=
puts are stable; Data bus inputs are floating
Active standby current: All device banks open;
t
mands; Other control and address bus inputs are switching; Data bus
inputs are switching
Operating burst write current: All device banks open; Continuous
burst writes; BL = 4, CL = CL (I
(I
Address bus inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
read, I
MAX (I
mands; Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:
(I
trol and address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
RC (I
RAS MAX (I
DD
DD
DD
t
CK (I
),
),
) interval; CKE is HIGH, S# is HIGH between valid commands; Other con-
DD
t
t
RCD =
RP =
OUT
DD
DD
),
),
t
); CKE is LOW; Other control and address bus in-
RAS =
= 0mA; BL = 4, CL = CL (I
t
t
DD
RP (I
RP =
DD
t
RCD (I
), AL = 0;
),
t
DD
t
t
RP =
RAS MIN (I
RP (I
); CKE is HIGH, S# is HIGH between valid commands;
DD
DD
DD
); CKE is HIGH, S# is HIGH between valid commands;
t
RP (I
Specifications and Conditions – 256MB
t
CK =
t
); CKE is HIGH, S# is HIGH between valid com-
CK =
DD
DD
t
); CKE is HIGH, S# is HIGH between valid com-
DD
CK (I
t
); CKE is HIGH, S# is HIGH between valid
CK (I
128MB, 256MB, 512MB (x64, SR) 240-Pin DDR2 SDRAM UDIMM
), AL = 0;
DD
DD
DD
),
), AL = 0;
); REFRESH command at every
t
RC =
t
CK =
t
RC (I
t
CK =
t
CK (I
DD
t
CK =
t
CK =
),
t
t
DD
CK (I
CK =
t
RAS =
),
t
CK
t
CK (I
t
t
RAS =
DD
CK (I
t
OUT
CK =
t
DD4W
t
CK (I
CK =
),
12
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
t
DD
RAS MIN
t
= 0mA; BL =
DD
RAS =
),
t
DD
t
CK (I
RAS MAX
),
t
t
CK (I
); CKE is
RAS =
t
RC =
t
RFC
t
DD
RAS
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
);
);
Symbol
I
I
I
I
I
I
I
DD4W
I
I
DD2Q
DD2N
DD3N
I
I
DD2P
DD3P
DD4R
DD0
DD1
DD5
DD6
-80E/
1180
1100
-800
540
660
260
280
160
300
920
28
48
28
1000
-667
480
600
220
240
140
280
940
740
© 2003 Micron Technology, Inc. All rights reserved.
28
48
28
I
DD
-53E
Specifications
440
540
180
200
120
240
820
780
700
28
48
28
-40E
440
520
160
180
100
200
640
620
680
28
48
28
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA