MT36LSDF12872G-133D1 Micron Technology Inc, MT36LSDF12872G-133D1 Datasheet
MT36LSDF12872G-133D1
Specifications of MT36LSDF12872G-133D1
Related parts for MT36LSDF12872G-133D1
MT36LSDF12872G-133D1 Summary of contents
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... Column addressing Module ranks PDF: 09005aef807da15c/Source: 09005aef80f69382 SDF36C64_128x72G.fm - Rev. E 10/05 EN Products and specifications discussed herein are subject to change by Micron without notice. 512MB, 1GB (x72, ECC, DR): 168-Pin SDRAM RDIMM www.micron.com/modules Figure 1: Height Standard 1.70in. (43.18mm) Options • Package 168-pin DIMM (standard) 168-pin DIMM (lead-free) • ...
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... MT36LSDF12872G-133__ MT36LSDF12872Y-133__ Note: The designators for component and PCB revision are the last two characters of each part number. Consult factory for current revision codes. Example: MT36LSDF12872G-133D1. PDF: 09005aef807da15c/Source: 09005aef80f69382 SDF36C64_128x72G.fm - Rev. E 10/05 EN 512MB, 1GB (x72, ECC, DR): 168-Pin SDRAM RDIMM Module Density ...
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Pin Assignments and Descriptions Table 4: Pin Assignment 168-Pin DIMM Front Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol CB1 DQ0 ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbol order; refer to Pin Assignment table on page 3 for more information Pin Number Symbol 27, 111, 115 RAS#, CAS#, 42, 79, 125, 163 CK0–CK3 128 CKE0–1 30, 45, ...
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... Functional Block Diagram Per industry standard, Micron modules utilize various component speed grades, as ref- erenced in the module part number guide at Standard modules use the following SDRAM devices: MT48LC32M4A2FB (512MB); MT48LC64M4A2FB (1GB). Lead-free modules use the following SDRAM devices: MT48LC32M4A2BB (512MB) ...
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Figure 3: Functional Block Diagram RS0# RS1# RS2# RS3# CKE0 A0–A11 (512MB) A0–A12 (1GB) DQMB0–DQMB7 10K V DD REGE PLL CLK Note: All resistor values are 10Ω unless otherwise specified. PDF: 09005aef807da15c/Source: 09005aef80f69382 SDF36C64_128x72G.fm - Rev. E 10/05 EN 512MB, ...
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... READ or WRITE command are used to select the starting column location for the burst access. SDRAM modules provide for programmable read or write locations, or full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. ...
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System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), ...
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A1–A9, A11 when A2–A9, A11 when and by A3–A9, A11 when The remaining (least significant) address bit(s) is (are) used to select the starting location within ...
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Table 6: Burst Definition Table Full page (y) Notes: 1. For full-page accesses 2,048. 2. For A0–A9, A11 will select the block of two burst; A0 selects the starting column within the block. 3. For ...
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Figure 5: CAS Latency Diagram CLK COMMAND DQ CLK COMMAND DQ Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit ...
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Write Burst Mode When programmed via M0–M2 applies to both READ and WRITE bursts; when the programmed BL applies to READ bursts, but write accesses are single- location (nonburst) accesses. Table 7: CAS ...
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Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of ...
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Table 11: I Specifications and Conditions – 512MB DD SDRAM components only; notes 11, 13; notes appear on pages 17 and 18; V Parameter/Condition Operating current: Active mode; Burst = 2; READ or WRITE ...
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Table 14: SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions Notes 11, 32; notes appear on pages 17 and 18 AC Characteristics Parameter Access time from CLK (positive edge) Address hold time Address setup time ...
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Table 15: AC Functional Characteristics Notes 11; notes appear on pages 17 and 18 Parameter READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit ...
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Notes 1. All voltages referenced This parameter is sampled. V test biased at 1.4V with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are ...
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... ECC, DR): 168-Pin SDRAM RDIMM t WR, and PRECHARGE commands). CKE may 7.5ns; for -13E and t RAS used in -13E speed grade modules is calculated from Micron Technology, Inc., reserves the right to change products or specifications without notice. 18 Notes t RP) begins at 7ns for -13E; ...
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PLL and Register Specifications Table 16: Register Timing Requirements and Switching Characteristics Register Symbol f clock t Propagation delay, Single rank pd1 SSTL t Propagation delay, Dual rank pd2 bit pattern by JESD82 Table ...
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... The system used for experimental purposes is a dual-processor 600 MHz work station, fully loaded with four MT36LSDT12872G modules. Case temperatures charted represent worst-case component locations on modules installed in the internal slots of the system. 3. Temperature versus air speed data is obtained by performing experiments with the system motherboard removed from its case and mounted in a Eiffel-type low air speed wind tun- nel ...
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Serial Presence-Detect SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 7, and Figure ...
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Figure 8: Definition of Start and Stop SCL SDA Figure 9: Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver Table 18: EEPROM Device Select Code The most significant bit (b7) is sent first ...
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Figure 10: SPD EEPROM Timing Diagram SCL t SU:STA SDA IN SDA OUT PDF: 09005aef807da15c/Source: 09005aef80f69382 SDF36C64_128x72G.fm - Rev. E 10/05 EN 512MB, 1GB (x72, ECC, DR): 168-Pin SDRAM RDIMM HIGH LOW t HD:STA ...
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Table 20: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage 3mA OUT Input leakage current: ...
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Table 22: Serial Presence-Detect Matrix “1”/”0”: Serial data, “driven to HIGH”/”driven to LOW”; V Byte Description 0 Number of bytes used by Micron 1 Total number of SPD memory bytes 2 Memory type 3 Number of row addresses 4 Number ...
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Table 22: Serial Presence-Detect Matrix (continued) “1”/”0”: Serial data, “driven to HIGH”/”driven to LOW”; V Byte Description 41 Device minimum active/auto refresh time, 42–61 Reserved 62 SPD revision 63 Checksum for bytes 0–62 64 Manufacturer’s JEDEC ID code 65-71 Manufacturer’s ...
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Module Dimensions All dimensions are in inches (millimeters); Figure 11: 168-Pin DIMM Dimensions U1 U2 0.079 (2.00) R (2X) U11 U12 0.118 (3.00) (2X) 0.118 (3.00) TYP 0.250 (6.35) TYP PIN 1 0.118 (3.00) TYP U28 U27 U36 U35 PIN ...