MT18VDDT6472G-265G3 Micron Technology Inc, MT18VDDT6472G-265G3 Datasheet - Page 8

• Manufacturer Part Number: MT18VDDT6472G-265G3
• Description: MODULE SDRAM DDR 512MB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDT6472G-265G3

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 266MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

General Description
MT18VDDT12872, and MT18VDDT25672 are high-
speed
512MB, 1GB, and 2GB memory modules organized in
x72 (ECC) configuration. DDR SDRAM modules use
internally configured quad-bank DDR SDRAM devices.
tecture to achieve high-speed operation. The double
data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single
read or write access for the DDR SDRAM module effec-
tively consists of a single 2n-bit wide, one-clock-cycle
data transfer at the internal SDRAM core and two cor-
responding n-bit wide, one-half-clock-cycle data
transfers at the I/O pins.
externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for
WRITEs.
clock inputs (CK and CK#); the crossing of CK going
HIGH and CK# going LOW will be referred to as the
positive edge of CK. Commands (address and control
signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and out-
put data is referenced to both edges of DQS, as well as
to both edges of CK.
are burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select device bank; A0–A11
(256MB) or A0–A12 (512MB, 1GB), or A0–A13 (2GB)
select device row). The address bits registered coinci-
dent with the READ or WRITE command are used to
select the device bank and starting device column
location for the burst access.
READ or WRITE burst lengths of 2, 4, or 8 locations. An
auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of
the burst access.
pdf: 09005aef808a331f, source: 09005aef80858037
DD18C32_64_128_256x72G.fm - Rev. E 9/04 EN
The
DDR SDRAM modules use a double data rate archi-
A bidirectional data strobe (DQS) is transmitted
DDR SDRAM modules operate from differential
Read and write accesses to DDR SDRAM modules
DDR SDRAM modules provide for programmable
CMOS, dynamic
MT18VDDT3272,
random-access,
MT18VDDT6472,
256MB,
256MB, 512MB, 1GB, 2GB (x72, ECC, SR)
8
SDRAM modules allows for concurrent operation,
thereby providing effective high bandwidth by hiding
row precharge and activation time.
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2, Class II compatible.
information regarding DDR SDRAM operation, refer to
the 128Mb, 256Mb, 512MB, or 1Gb DDR SDRAM com-
ponent data sheets.
PLL and Register Operation
where the command/address input signals are latched
in the registers on the rising clock edge and sent to the
DDR SDRAM devices on the following rising clock
edge (data access is delayed by one clock cycle). A
phase-lock loop (PLL), on the module, receives and
redrives the differential clock signals (CK, CK#) to the
DDR SDRAM devices. The registers and PLL minimize
system and clock loading.
Serial Presence-Detect Operation
detect (SPD). The SPD function is implemented using
a 2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard I
using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/EEPROM addresses. Write protect (WP) is tied
to ground on the module, permanently disabling hard-
ware write protect.
Mode Register Definition
mode of operation of DDR SDRAM devices. This defi-
nition includes the selection of a burst length, a burst
type, a CAS latency and an operating mode, as shown
in Figure 5, Mode Register Definition Diagram, on
page 9.
MODE REGISTER SET command (with BA0 = 0 and
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power (except
for bit A8, which is self-clearing).
The pipelined, multibank architecture of DDR
An auto refresh mode is provided, along with a
DDR SDRAM modules operate in registered mode,
DDR SDRAM modules incorporate serial presence-
The mode register is used to define the specific
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM RDIMM
The mode register is programmed via the
©2004 Micron Technology, Inc. All rights reserved.
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2
C bus