MT18VDDT6472AG-262G4 Micron Technology Inc, MT18VDDT6472AG-262G4 Datasheet - Page 24

• Manufacturer Part Number: MT18VDDT6472AG-262G4
• Description: MODULE SDRAM DDR 512MB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18VDDT6472AG-262G4

• Memory Type: DDR SDRAM
• Memory Size: 512MB
• Speed: 266MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

pdf: 09005aef808a331f, source: 09005aef80858037
DD18C32_64_128_256x72G.fm - Rev. E 9/04 EN
31. READs and WRITEs with auto precharge are not
32. Any positive glitch in the nominal voltage must be
33. Normal Output Drive Curves:
160
140
120
100
80
60
40
20
Figure 9: Pull-Down Characteristics
0
0.0
allowed to be issued until
fied prior to the internal precharge command
being issued.
less than 1/3 of the clock and not more than
+400mV or 2.9V, whichever is less. Any negative
glitch must be less than 1/3 of the clock cycle and
not exceed either -300mV or 2.2V, whichever is
more positive.
a. The full variation in driver pull-down current
b. The variation in driver pull-down current
c. The full variation in driver pull-up current
d. The variation in driver pull-up current within
e. The full variation in the ratio of the maximum
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 9,
Pull-Down Characteristics.
within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 9, Pull-Down Characteristics.
from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 10,
Pull-Up Characteristics.
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
10, Pull-Up Characteristics.
to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
0.5
1.0
V
V
OUT
OUT
(V)
(V)
t
RAS (MIN) can be satis-
1.5
2.0
Minimum
256MB, 512MB, 1GB, 2GB (x72, ECC, SR)
2.5
24
34. The voltage levels used are derived from a mini-
35. V
36. V
37.
38.
39. During initialization, V
40. The current Micron part operates below the slow-
41. For -262, -26A, and -265, I
42. Random address changing and 50 percent of data
-100
-120
-140
-160
-180
-200
-20
-40
-60
-80
0
Figure 10: Pull-Up Characteristics
0.0
mum V
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.
pulse width
greater than 1/3 of the cycle rate. V
V
pulse width can not be greater than 1/3 of the
cycle rate.
t
t
over
t
referenced to a specific voltage level but specify
when the device output is no longer driving
(
be equal to or less than V
V
even if V
42
supply and the input pin.
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
35mA per DDR SDRAM device at 100 MHz.
changing at every transfer.
f. The full variation in the ratio of the nominal
HZ (MAX) will prevail over
RPST (MAX) condition.
RPST end point and
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
IL
DD
RPST), or begins driving (
TT
184-PIN DDR SDRAM RDIMM
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.
(MIN) = -1.5V for a pulse width
overshoot: V
and V
may be 1.35V maximum during power up,
t
of series resistance is used between the V
DQSCK (MIN) +
DD
DD
0.5
DD
level and the referenced test load. In
/V
Q must track each other.
DD
3ns and the pulse width can not be
Q are 0V, provided a minimum of
IH
1.0
V
(MAX) = V
DD Q
t
RPRE (MAX) condition.
t
RPRE begin point are not
- V
DD
©2004 Micron Technology, Inc. All rights reserved.
OUT
DD
t
Q, V
DD
t
LZ (MIN) will prevail
(V)
RPRE).
1.5
+ 0.3V. Alternatively,
3
N
TT
t
DD
DQSCK (MAX) +
is specified to be
, and V
Q + 1.5V for a
IL
undershoot:
3ns and the
2.0
REF
must
TT
2.5