MT18VDDF12872DG-335D3 Micron Technology Inc, MT18VDDF12872DG-335D3 Datasheet - Page 12
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MT18VDDF12872DG-335D3
Manufacturer Part Number
MT18VDDF12872DG-335D3
Description
MODULE SDRAM DDR 1GB 184DIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT18VDDF12872DG-335D3.pdf
(17 pages)
Specifications of MT18VDDF12872DG-335D3
Memory Type
DDR SDRAM
Memory Size
1GB
Speed
333MT/s
Package / Case
184-DIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
184RDIMM
Device Core Size
72b
Organization
128Mx72
Total Density
1GByte
Chip Density
512Mb
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.62A
Number Of Elements
18
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
184
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 11:
PDF: 09005aef807eb17d/Source: 09005aef807d24c9
ddf18c64_128x72d.fm - Rev. D 10/08 EN
Parameter/Condition
Operating one bank active-precharge current:
t
Address and control inputs changing once every two clock cycles
Operating one bank active-read-precharge current: BL = 2;
t
changing once per clock cycle
Precharge power-down standby current: All device banks idle;
Power-down mode;
Idle standby current: CS# = HIGH; All device banks idle;
t
once per clock cycle; V
Active power-down standby current: One device bank active; Power-
down mode;
Active standby current: CS# = HIGH; CKE = HIGH; One device bank
active
changing twice per clock cycle; Address and other control inputs
changing once per clock cycle
Operating burst read current: BL = 2; Continuous burst reads; One
device bank active; Address and control inputs changing once per clock
cycle;
Operating burst write current: BL = 2; Continuous burst writes; One
device bank active; Address and control inputs changing once per clock
cycle;
cycle
Auto refresh current
Self refresh current: CKE ≤ 0.2V
Operating bank interleave read current: Four device bank
interleaving reads (BL = 4) with auto precharge;
t
READ or WRITE commands
CK =
RC =
CK =
CK =
t
t
t
;
t
t
t
RC (MIN);
CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;
CK (MIN); CKE = HIGH; Address and other control inputs changing
CK =
CK (MIN); Address and control inputs change only during active
CK =
t
RC =
t
t
CK (MIN); I
CK (MIN); DQ, DM, and DQS inputs changing twice per clock
t
t
I
Values are for the MT46V64M8 DDR SDRAM only and are computed from values specified in the
512Mb (64 Meg x 8) component data sheet
RAS (MAX);
CK =
DD
t
CK =
Specifications and Conditions – 1GB
Notes:
t
CK (MIN); CKE = LOW
t
CK =
IN
t
CK (MIN); I
OUT
= V
t
t
CK =
CK (MIN); CKE = LOW
REF
= 0mA
1. Value calculated as one module rank in this operating condition; all other module ranks are
2. Value calculated reflects all module ranks in this operating condition.
for DQ, DM, and DQS
in I
t
CK (MIN); DQ, DM, and DQS inputs
OUT
DD
2P (CKE LOW) mode.
= 0mA; Address and control inputs
512MB, 1GB (x72, ECC, DR) 184-Pin DDR SDRAM RDIMM
t
RC =
t
RC =
t
t
RFC =
RFC = 7.8125µs
t
RC (MIN);
t
RC (MIN);
t
12
RFC (MIN)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
3N
5A
4R
2P
2F
3P
0
1
5
6
7
1
1
2
2
1
2
2
2
1
2
2
1
1,440
1,710
1,080
1,755
1,800
6,210
4,095
-40B
990
810
198
90
90
Electrical Specifications
1,215
1,485
1,530
1,620
5,220
3,690
-335
810
630
900
180
90
90
©2004 Micron Technology, Inc. All rights reserved
1,215
1,485
1,530
1,440
5,220
3,645
-262
810
630
800
180
90
90
-26A/
1,080
1,350
1,350
1,260
5,040
3,195
-265
720
540
810
180
90
90
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA