MT16LSDF6464HG-13ED2 Micron Technology Inc, MT16LSDF6464HG-13ED2 Datasheet - Page 7

• Manufacturer Part Number: MT16LSDF6464HG-13ED2
• Description: MODULE SDRAM 512MB 144SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16LSDF6464HG-13ED2

• Memory Type: SDRAM
• Memory Size: 512MB
• Speed: 133MHz
• Package / Case: 144-SODIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

General Description
are high-speed CMOS, dynamic random-access
256MB and 512MB unbuffered memory modules,
organized in x64 configurations. These modules use
internally configured quad-bank SDRAMs with a syn-
chronous interface (all signals are registered on the
positive edge of the clock signal CK).
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select the device bank, A0–A11
[256MB] or A0–A12 [512MB] select the device row).
The address bits A0–A9 (for both 256MB and 512MB
modules) registered coincident with the READ or
WRITE command are used to select the starting device
column location for the burst access.
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence.
ture to achieve high-speed operation. This architec-
ture is compatible with the 2n rule of prefetch
architectures, but it also enables the column address
to be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one device
bank while accessing one of the other three device
banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
power memory systems. An auto refresh mode is pro-
vided, along with a power-saving, power-down mode.
All inputs and outputs are LVTTL-compatible.
DRAM operating performance, including the ability to
synchronously burst data at a fast data rate with auto-
matic column-address generation, the ability to inter-
leave between internal banks in order to hide
precharge time and the capability to randomly change
column addresses on each clock cycle during a burst
access. For more information regarding SDRAM opera-
tion, refer to the 128Mb or 256Mb SDRAM component
data sheets.
pdf: 09005aef807924d2, source: 09005aef807924f1
SDF16C32_64x64HG.fm - Rev. E 4/06 EN
The MT16LSDF3264(L)H and MT16LSDF6464(L)H
Read and write accesses to the SDRAM modules are
These modules provide for programmable READ or
These modules use an internal pipelined architec-
These modules are designed to operate in 3.3V, low-
SDRAM modules offer substantial advances in
7
Serial Presence Detect Operation
(SPD). The SPD function is implemented using a
2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes are programmed
by Micron to identify the module type, SDRAM charac-
teristics and module timing parameters. The remain-
ing 128 bytes of storage are available for use by the
customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM
device (DIMM) occur via a standard I
DIMM’s SCL (clock) and SDA (data) signals, together
with SA[2:0], which provide eight unique DIMM/
EEPROM addresses. Write protect (WP) is tied to
ground on the module, permanently disabling hard-
ware write protect.
Initialization
predefined manner.
than those specified may result in undefined opera-
tion. When power is applied to V
taneously), and the clock is stable (stable clock is
defined as a signal cycling within timing constraints
specified for the clock pin), the SDRAM requires a
100µs delay prior to issuing any command other than a
COMMAND INHIBIT or NOP . Starting at some point
during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT
or NOP commands should be applied.
least one COMMAND INHIBIT or NOP command hav-
ing been applied, a PRECHARGE command should be
applied. All device banks must then be precharged,
thereby placing the device in the all banks idle state.
must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for mode register
programming. Because the mode register will power
up in an unknown state, it should be loaded prior to
applying any operational command.
Mode Register Definition
mode of operation of the SDRAM. This definition
includes the selection of a burst length, a burst type, a
CL, an operating mode, and a write burst mode, as
shown in Figure 4 on page 8. The mode register is pro-
grammed via the LOAD MODE REGISTER command
and will retain the stored information until it is pro-
grammed again or the device loses power.
These modules incorporate serial presence-detect
SDRAMs must be powered up and initialized in a
When the 100µs delay has been satisfied with at
When in the idle state, two AUTO REFRESH cycles
The mode register is used to define the specific
Micron Technology, Inc., reserves the right to change products or specifications without notice.
144-PIN SDRAM SODIMM
256MB, 512MB (x64, DR)
Operational procedures other
©2006 Micron Technology, Inc. All rights reserved.
DD
and V
2
C bus using the
DD
Q (simul-