MT9VDDF3272Y-40BG3 Micron Technology Inc, MT9VDDF3272Y-40BG3 Datasheet - Page 4

• Manufacturer Part Number: MT9VDDF3272Y-40BG3
• Description: MODULE DDR SDRAM 256MB 184-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9VDDF3272Y-40BG3

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6:
PDF: 09005aef8082c948/Source: 09005aef807d56a1
ddf9c32_64x72.fm - Rev. C 10/08 EN
RAS#, CAS#, WE#
DQS0–DQS8
DQ0–DQ63
DM0–DM8
CK0, CK0#
V
BA0, BA1
SA0–SA2
CB0–CB7
Symbol
A0–A12
RESET#
DD
V
CKE0
Pin Descriptions
SDA
DDSPD
V
S0#
SCL
V
NC
/V
REF
SS
DD
Q
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
–
256MB, 512MB (x72, ECC, SR) 184-Pin DDR SDRAM RDIMM
Description
Address inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by BA0 and BA1)
or all device banks (A10 HIGH). The address inputs also provide the op-code
during a MODE REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded during the LOAD
MODE REGISTER command.
Bank address: BA0 and BA1 define the device bank to which an ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
Clock: CK and CK# are differential clock inputs. All control, command, and
address input signals are sampled on the crossing of the positive edge of CK
and the negative edge of CK#. Output data (DQ and DQS) is referenced to the
crossings of CK and CK#.
Clock enable: CKE enables (registered HIGH) and CKE disables (registered
LOW) the internal clock, input buffers, and output drivers.
Input data mask: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH, along with that input data, during a write
access. DM is sampled on both edges of DQS. Although the DM pins are input-
only, the DM loading is designed to match that of the DQ and DQS pins.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command
being entered.
Reset: Asynchronously forces all registered outputs LOW when RESET# is LOW.
This signal can be used during power-up to ensure that CKE is LOW and DQ are
High-Z.
Chip selects: S# enables (registered LOW) and disables (registered HIGH) the
command decoder.
Presence-detect address inputs: These pins are used to configure the SPD
EEPROM address range on the I
Serial clock for SPD EEPROM: SCL is used to synchronize the presence-detect
data transfer to and from the module.
Check bits.
Data input/output: Data bus.
Data strobe: Output with read data. Edge-aligned with read data. Input with
write data. Center-aligned with write data. Used to capture data.
Serial data: SDA is a bidirectional pin used to transfer addresses and data into
and out of the presence-detect portion of the module.
Power supply: +2.5V ±0.2V (-40B: +2.6V ±0.1V).
SPD EEPROM power supply: +2.3V to +3.6V.
SSTL_2 reference voltage (V
Ground.
No connect: These pins are not connected on the module.
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
/2).
Pin Assignments and Descriptions
2
C bus.
©2002 Micron Technology, Inc. All rights reserved.